Application of a Generative Grammar for the Automated Architectural Exploration of Digital System-on-Chip (SoC) Platforms

• Applicant: Professor Dr.-Ing. Ulf Schlichtmann
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2013 to 2016
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 231839943

Embedded systems are found in many technical applications, ranging from household devices, consumer electronics to the control and surveillance of trains or industrial robots. They are known as the hidden champions of the industry because their growing computational power made various innovations possible in the past and will make even more possible in the future. The resulting rise in complexity of these systems, as well as the integration on a single silicon die as system-on-chip or short SoC, calls for new design methods for tomorrows systems. For this, a fast SoC realization can be achieved by a platform-based design flow. This requires that existing modules, so called intellectual property blocks, are created to form a SoC platform. This platform must exhibit the ability to be configurable to adapt to new requirements and specifications. Today, this construction and configuration of the platform architecture is often done manually. This limits the efficiency because only a limited number of configurations can be investigated.In this project, a novel and highly efficient approach to support the platform architecture construction step during the synthesis of the system will be developed. For the optimization of the architecture, the application of so-called generative grammars and search methods from artificial intelligence will be investigated, which have never been applied in this context. This automation poses a challenging optimization problem because the topology of the system is altered and discrete parameters must be optimized. This methodology promises a very formal description of the topological changes during the optimization of the platform architecture, which is comprehensive to the user and allows interactive control, if this is wished. The efficiency of the method will be investigated on the platform-based design of a subsystem that is based on the open source Wishbone bus specification and OpenRISC processor architecture from OpenCores. The results of this research project will also be of interest for other disciplines since similar optimization problems with discrete parameters and topological changes can be found in many other scientific and technical fields.

• DFG Programme: Research Grants