Fastest Digital-to-Analog-Converter with low power consumption in FDSOI-CMOS Technology for Ultra-Broadband Data Transmission

• Applicant: Professor Dr.-Ing. Manfred Berroth
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering ; Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2015 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 276016065

In the first project period of two years with the topic “Ultrafast digital-to-analog converters in FDSOI CMOS for ultra-broadband communication” new circuit topologies for ultrafast and high bandwidth digital-to-analog converters (DACs) in CMOS technology have been investigated. The research activities culminated in the design of a 128 GS/s 8 bit DAC demonstrator IC including a 256 kByte on-chip memory in a 28 nm FDSOI CMOS technology which has been assigned for tape-out.Concerning new topologies, a voltage-based 8 bit segmented DAC core with conversion rates up to 64 GS/s has to be mentioned at first. The DAC output consists of 15 unary output stages for the four MSBs and a binary weighted network for the four LSBs. One unary output stage consists of a CMOS inverter and a series resistance. The binary weighted part consists of four CMOS inverters and a four-stage R-2R network. The implemented DAC core shows the feasibility of ultrafast DAC cores in a voltage-based concept, and may replace traditional current-based approaches that need larger supply voltages. The low supply voltage of slightly above 1 V is the main advantage of this new architecture and is compatible with the core CMOS logic supply voltage. The power dissipation of the 64 GS/s core is only around 1,17 W. Another important innovative concept that is required for the realization of the 64 Gbit/s driver chains and the 32 GHz clock paths are CMOS inverter based driver chains with resistive negative feedback to increase the bandwidth. The second key component of the demonstrator IC is an analog multiplexer (AMUX) combining the output signals of the two 64 GS/s DAC cores by time interleaving to a single 128 GS/s output. Such a fast AMUX has been realized for the first time in CMOS technology within this project.In case of a successful demonstration of the 128 GS/s conversion rate, this IC would be the fastest monolithic electronic DAC to the best of the authors’ knowledge. Furthermore, the predicted output bandwidth of 32 GHz would be the highest one ever demonstrated in CMOS technology.The first aim of the project continuation is to start operation of the DAC and to characterize in detail the different parts of the IC and the output signal quality. As there are different linear and nonlinear effects in the implemented DAC chip which distort the output signal and reduce resolution, distortion compensation procedures shall be investigated and implemented to increase performance. Finally, different applications of the AWG module shall be demonstrated by applying these compensation methods. A broad spectrum of applications ranging from very broadband optical link signals to micro- and mm-wave signals, e.g. for mobile and data communication of the 5th generation (5G), will be demonstrated during this project.

• DFG Programme: Research Grants
• Co-Investigator: Dr.-Ing. Markus Grözing