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Project Details

Institution

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Universität Siegen
Department Elektrotechnik und Informatik
Research Group Digital Integrated Systems

Address Hölderlinstraße 3
57068 Siegen
Deutschland

57068 Siegen

Projects

Research Grants
- Current projects
  - Design Obfuscation with Sequential Timing to Counter Reverse Engineering
    (Applicants Li, Bing ; Schlichtmann, Ulf ; Sigl, Georg )
  - Exploring Efficient and Robust Optical Accelerators for Neural Networks
    (Applicant Schlichtmann, Ulf )
  - Learning-based Efficient and Accurate Timing Analysis of Integrated Circuits
    (Applicant Schlichtmann, Ulf )
  - Reliability and Robustness Enhancement of RRAM-based Neuromorphic Computing
    (Applicants Schlichtmann, Ulf ; Zhang, Li )

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