Actor-Oriented Synthesis and Optimization of Digital Hardware/Software Systems at System-Level

• Applicants: Professor Dr.-Ing. Christian Haubelt; Professor Dr.-Ing. Jürgen Teich
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2009 to 2016
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 101967358

The goal of this project is to sustainably improve the implementation of dataflow-dominated applications in the domain of embedded systems as heterogeneous multiprocessor system with respect to performance as well as energy and cost efficiency. For this purpose, novel methods for the synthesis and optimization of embedded systems at system-level are developed. Starting from an actor-oriented application description, approaches for automatic design space exploration are studied in order to identify solutions, which serve as starting point for model refinement and synthesis of optimal (partial) hardware and software solutions. As a first important step, domain-specific optimization and synthesis approaches have been studied during the first funding period. In particular, it has been shown that novel clustering methods for islands consisting of static dataflow actors allow for an accurate analysis and the minimization of timing properties, energy con-sumption, and cost. In the second funding period, those quality improving and complexity reducing system synthesis methods will be extended in many different ways: On the specification side, novel clustering methods for more general models, especially applications with dynamic actor behavior, will be studied. The clustering methods, which have been basically considered in the context of scheduling overhead reduction of single-processor software implementations, will be extended towards multi-processor target platforms. By this, a prescheduling of data traffic on the interconnection network is achieved, which is expected to significantly reduce the communication and arbitration overhead. Moreover, by applying clustering during high-level synthesis, and thus hardware synthesis, we propose a novel transactoral high-level synthesis methodology. In contrast to available tools, which often only permit the efficient synthesis of single actors, such a holistic synthesis of a complete cluster promises substantial energy and cost improvements (e.g., chip area). Finally, the clustering methods should be seamlessly supported during design space exploration. As a consequence, it is possible to benefit from the novel methods across hardware/software boundaries and, as a result, important implementation properties, e.g., performance, energy, and cost efficiency, are improved in an application-specific way. The methods, which are developed within this project, can be seen to be orthogonal to existing system synthesis approaches and serve as a new starting point to sustainably reduce the complexity in embedded systems design.

• DFG Programme: Research Grants