KArlsruhe's Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array (Kahrisma) Architecture

• Applicants: Professor Dr.-Ing. Jürgen Becker; Professor Dr.-Ing. Jörg Henkel
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2009 to 2014
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 113684250

Due to the diverse processing behavior and non-predictable run-time characteristics of the next generation applications future embedded devices may no longer perform efficiently when applying traditional design styles, e.g. when a design is tailor made at design time for a specific scenario or application domain. We strongly believe that crucial design decisions can no longer be fixed/determined at design time. This begets the demand for an innovative processor architecture reacting flexibly to runtime scenarios. Therefore, we propose a novel multi-grained adaptable hardware architecture, tightly integrating coarse and fine-grained reconfigurable fabrics extended by the capability to handle different Instruction Set Architectures (ISAs) in parallel. A flexible software framework is needed to make use of these novel features. Different ISAs require a retargetable compilation framework (based on an Architecture Description Language) while automatic multi-grained Custom Instruction detection will deliver optimized implementations for our multi-grained reconfigurable hardware accelerators. Additionally, an adaptive run-time system is required to efficiently distribute the available hardware resources between different applications and threads considering performance and power constraints. We believe that our novel concept will provide a promising paradigm for future adaptive embedded processing, targeting next generation applications.

• DFG Programme: Research Grants