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Characterization of Multi-core Processors for Power-Estimation at System-level

Subject Area Computer Architecture, Embedded and Massively Parallel Systems
Term from 2010 to 2014
Project identifier Deutsche Forschungsgemeinschaft (DFG) - Project number 166220900
 
Final Report Year 2015

Final Report Abstract

A new approach with focus on shared cache analysis was suggested for investigation of multicore processors. The main challenge of the project CoMPESys is how co-running applications in multicore system should be considered on order to estimate power consumption. For this reason a special methodology was needed which enables the analysis of the program contention due to shared resources in multicore system. The understanding of shared cache functionality during program execution and its impact to the total power is needed for development of an effective and accurate power estimation methodology. We have developed a cache simulator that provides cache statistics for both whole program traces and separate program phases. We analysed cache statistics over time because it reveals additional information about program behaviour that could be missed if we take into account misses only for the whole program execution. The optimal size of the program phase for analysis was defined for different types of applications from SPEC 2006 and Mediabench suites. We have suggested the characterisation methodology of embedded applications, which provides useful information for scheduling of applications on embedded multicore processors. Based on cache statistics we have defined which applications are allowed to be co-scheduled together without degradation of their performance and which are expected being affected by co-running and as a result increasing power consumption in the system. We studied the role of data sharing in performance of co-running applications. We considered shared cache lines which are allowed to be accessed during their lifetime by more than one program. It was found that these lines enable a reduction of miss rates in the last level cache as for embedded multimedia applications and for general purpose computing as well. This effect depends on L2 cache size and the program itself. Our experiments showed reduction in L2 cache misses due to shared cache lines up to 25% for Mediabench programs and up to 60% for SPEC CPU2006 applications. The most significant impact of data sharing was observed during initial phases of program execution. The effect of lower misses observed in our work can have a significant impact on performance and energy dissipation. The special characteristics of applications are needed to be defined in order to use this beneficial effect of data sharing. Knowledge about program contention due to shared resources is important for various design problems concerning multicore architectures. It is needed for power estimation, scheduling of parallel applications and design of shared memories. Moreover, deep understanding of programs behaviour is especially needed for the development of accurate models that are able to predict misses caused by shared resources in multicore architectures. It can be used for mapping of existing applications on multicore architectures and finally, for the development of new applications for multicore embedded systems, which utilize resources of the multicore architecture more efficiently. As embedded systems are usually designed to perform particular applications, the methodology of an early analysis of their co-execution is of special importance.

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