Root-Based Compensation Techniques of Memory Effects in Radio Frequency Power Amplifiers

• Applicant: Professor Dr.-Ing. Friedel Gerfers, since 5/2015
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2012 to 2015
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 219249625

Recent mobile communication standards make high demands on linearity and bandwidth of CMOS based transceivers and RF power amplifiers. Modern TX systems use digital pre-distortion (DPD) to achieve the required linearity as efficient as possible. Unfortunately, memory effects occurring in RF power amplifiers significantly reduce the performance of simple memory-less DPD concepts. As a counter-measure, memory polynomial DPD systems can be deployed. They are based on black-box models and can reduce the memory-effects to some extent. Anyhow, they are clearly more complex and the computational effort is increased. Thus, they require a larger area and have larger power consumption compared to their memory-less counterparts.Our research project therefore aims to consider memory effects already in the power amplifier's circuit design phase. By enhanced knowledge of the physical roots, the memory effects shall be reduced and compensated effectively. For this reason, our aim is to develop a methodology for "memory aware design" which is suitable for the various power amplifier topologies. Part of this methodology is the mapping of significant properties of time-domain measured AM/AM and AM/PM trajectories to their physical root cause, mostly independent of the PA's actual topology. By means of aligned design methods and novel circuit design concepts, the memory effects are reduced and compensated with a suitable circuit.Within the first 19 month of our project, we further enhanced and improved the existing time domain measurement systems. A novel electro-thermal coupled simulation concept was introduced into the circuit design framework and allows mutual evaluation of both electrical and thermal memory effects. First compensation strategies have been found and investigated within simulations and measurements. The development of the actual compensation circuit consolidates the technical expertise gathered within the preliminary studies. By integrating on- and off-chip sensors for various purposes, both electrical and thermal effects can be addressed. Next to direct compensation within the PA, such sensors can also assist in compensation mechanisms within the digital baseband. An extensive test concept guarantees accessibility to all required nodes within the circuit. Thus, it allows comprehensive analysis of the developed concepts.Altogether, the acquired approaches and the novel compensation circuit will offer a very efficient way to reduce memory effects - without the need of memory-polynomials or other more complex methods. This finally allows further integration of CMOS power amplifiers, even in single-chip transceivers, as cost-efficient alternative to III-V based semiconductor technologies.

• DFG Programme: Research Grants
• Ehemaliger Antragsteller: Professor Dr.-Ing. Heinrich Klar, until 5/2015 (†)