Novel Computer-Architectural Concepts Arising from Complementary Resistive Switch Enhanced Passive Crossbar Arrays

• Applicant: Dr.-Ing. Eike Linn
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2013 to 2016
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 237378502

The goal of this project is to elaborate novel beyond memory application fields for ultimately scalable passive crossbar arrays. Starting from existing concepts of realizing logic operations with single resistive switches, novel crossbar logic concepts and concepts suitable for neuromorphic computing will be developed.Passive crossbar arrays allow for extremely high packing density, but appropriate selector devices are required to prevent parasitic current paths. Especially the use of complementary resistive switches (CRSs), i.e. two anti-serially connected resistive switches, is a favorable selection device paradigm, which will be applied in this project mainly to achieve sufficiently large arrays. The main focus of the project is the exploration of novel crossbar logic approaches for passive crossbar arrays. The challenge will be to expand logic concepts to obtain full array compatible concepts which allow for highly parallel operations. On this basis, CRS-based multi-array approaches will be investigated to find best throughput solutions. Content addressable memories or associative arrays based on crossbar arrays will be considered in order to expand applications to neuromorphic computing, paving the way to highly area efficient and low power pattern recognition systems.An important objective of this project will be the comparison of the novel concepts to corresponding CMOS implementations in terms of performance. To obtain significant results from the simulation of the logic operations within the array, accurate dynamical (memristive) models are required. Three prototypical resistive switch classes, electro-chemical metallization mechanism (ECM) devices, valence change mechanism (VCM) devices and magnetic tunnel junction (MTJ) devices, will be considered. The physical device models will be adopted and implemented for circuit simulation with SPICE. In the simulation, the dynamical models will either be connected to serial selector elements or will be connected anti-serially for realization of complementary resistive switches. By doing so, logic operations in crossbar memories can be simulated and the performance in terms of energy and processing speed can be determined directly. The novel logic-in-array concepts as well as the associative memory concepts for neuromorphic computing will be evaluated within this framework. Furthermore, the multi-array concepts will be simulated, and the expected increase in efficiency of the logic operations will be studied.In the last step, area consumption, energy consumption, and operation speed of the best logic-in-array concept will be compared to the performance of ultimately scaled CMOS.

• DFG Programme: Research Grants