Project Details
Projekt
Real100G.com: Mixed Mode Baseband for 100 Gbps Wireless Communication
Applicants
Professor Dr.-Ing. Ingmar Kallfass; Professor Dr.-Ing. Rolf Kraemer; Professor Dr.-Ing. Christoph Scheytt
Subject Area
Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Term
from 2013 to 2020
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 237428798
The project Real100G.com aims at achieving 100 Gbps wireless communication with an ultra-high RF bandwidth (50 GHz), moderate spectral efficiency (2 to 4 b/s/Hz), and a carrier frequency at high millimeter-wave frequencies around 240 GHz. We pursue this system approach for both first and second phase, focusing on system design investigations, baseband signal processing, and synchronization. Major challenges of all future 100 Gbps wireless systems will be the extreme signal processing power, complexity, and power dissipation of the baseband processor. Furthermore, in our approach the use of ultra-high RF bandwidth results in extreme bandwidth requirements (25 GHz) for the baseband processor. Our research focuses on analog/mixed-signal baseband processing and is based on the assumption that an intelligent mixture of analog and digital signal processing has the potential to outperform purely digital signal processing in terms of power dissipation and hardware complexity and eventually cost. We chose Parallel-Spread-Spectrum Sequencing (PSSS) as an analog-friendly modulation and coding scheme that allows for an efficient analog/mixed-signal implementation of a 100 Gbps wireless baseband processor. Furthermore, analog/mixed-signal RF synchronization schemes are investigated for similar reasons. In the first phase we have focused on 100 Gbps PSSS system design, PSSS receiver baseband processor design, and RF synchronization. We already successfully demonstrated 40 Gbps PSSS-modulated data transmission at 240 GHz carrier frequency and validated core circuits of our mixed-signal baseband processor and synchronization scheme in hardware. In the second phase of the SPP we want to continue this successful path and add new components to our 100 Gbps transceiver, e. g. the PSSS transmitter baseband processor. Furthermore, some interesting new topics emerged from our research in the first phase such as investigations on PSSS signal clipping and spectral shaping, as well as alternative synchronization techniques. We plan to continue our cooperation with the projects Real100G.rf (Zwick, Pfeiffer) and End2End100 (Nolte, Kraemer) which resulted already in an overall system design and want to perform extended joint transmission experiments at the end of the 2nd phase of the SPP targeting for a complete 100 Gbps wireless system demonstration.
DFG Programme
Priority Programmes
