GALS Methodology for Substrate Noise Reduction in BiCMOS technologies- GASEBO
Final Report Abstract
The main goal of this project was to investigate the possibility of using GALS as a low-noise design approach for substrate noise reduction in mixed-signal integrated circuits in BiCMOS technologies, i.e. in lightly doped substrates. In order to be able to analyze GALS-based methodologies for substrate noise reduction in lightly doped substrates, the connection between the simultaneous switching activity and the generated substrate noise in such substrates was analyzed, and a simplified numerical model describing substrate noise propagation was developed. The plesiochronous GALS frequency scheme was chosen as the most suitable for substrate noise reduction. Two substrate noise reduction methodologies were developed: Harmonic-balanced plesiochronous GALS partitioning methodology, applicable for systems where on-chip parasitics are negligible compared to package parasitics. Theoretically it can provide a spectral peak attenuation of 20log(𝑀), and it enables targeting also higher harmonics for substrate noise reduction. The method can also be combined with power-balanced plesiochronous GALS partitioning. - Harmonic/area based or power/area based plesiochronous GALS partitioning methodology with power domain separation, applicable for systems where power domain separation is possible. This method also takes floorplanning into account. Achievable spectral peak attenuation depends on the number of supply/ground package pins, on substrate resistivity and chip dimensions. Both methodologies were theoretically analyzed, and for both of them an optimization algorithm was developed and numerically evaluated in MATLAB. For harmonic balanced plesiochronous GALS partitioning methodology, the algorithm was also embedded in EMIAS noise analysis tool, and tested on a real design example in this tool. The corresponding test chips have been designed in the project and the tests will be finalized soon. As a consequence of the GASEBO project the methodology for low-noise GALS partitioning has been introduced, which could be also utilized in the relevant application circuits. As a consequence, we could estimate the results as very positive and GASEBO project as successful.
Publications
- “A coarse model for estimation of switching noise in lightly doped substrates”, Proc. of 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 217-222, Belgrade, Serbia 2015
Milan Babic, Milos Krstic
(See online at https://doi.org/10.1109/DDECS.2015.27) - “Frequency-domain modeling of ground bounce and substrate noise in lightly doped substrates”, Proc. of 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Salvador, Bahia, Brazil 2015
Milan Babic, Xin Fan, Milos Krstic
(See online at https://doi.org/10.1109/PATMOS.2015.7347597) - “GALS methodology for substrate noise reduction in BiCMOS technologies”, Proc. of Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), pp. 46-47, Tallinn, Estonia 2015
Milan Babic, Milos Krstic
- “Modeling of substrate noise coupling and ground bounce for GALS systems”, Proc. of the Annual DCPS (Dependable Cyber-Physical Systems) Evaluation Workshop, pp. 70-73, Cottbus, Germany 2015
Milan Babic, Milos Krstic
- “GALS partitioning methodology for substrate noise reduction in mixed-signal integrated circuits”, Proc. of 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 67-74, Porto Alegre, Brazil 2016
Milan Babic, Steffen Zeidler, Milos Krstic
(See online at https://doi.org/10.1109/ASYNC.2016.15) - Reducing Switching Noise Effects by Advanced Clock Management, 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, EMC Compo 2017
M. Krstic, X. Fan, M. Babic, E. Grass, T. Bjerregaard, A. Yakovlev
(See online at https://doi.org/10.1109/EMCCompo.2017.7998072) - “A substrate noise reduction methodology based on power domain separation of GALS subcomponents”, Proc. of 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki, Greece 2017
Milan Babic, Milos Krstic
(See online at https://doi.org/10.1109/PATMOS.2017.8106981)
