Design of efficient 3D integrated DRAM subsystem architectures based on detailed designspace explorations and modeling
Final Report Abstract
The ever increasing importance of the DRAM subsystem attached to HPC or embedded computing systems fosters the modeling of DRAM subsystems on different abstraction levels. In 3D-DRAM subsystems the proximity to the underlying SoC in the stack increases the need to have detailed models in terms of bank level architectures and improved detailed DRAM power models to cope with thermal issues. In this project, we investigated new modeling techniques on system-level (ESL) with a holistic simulation framework (DRAMSys) and on architecture-level (DRAMSpec) that uses as abstraction level the DRAM bank. The improved DRAMPower modeling tool permits exhaustive DSEs and various investigations on 3D-DRAMs, Low-Power-DRAMs, commodity DRAMs, and many other DRAM types. DRAMPower and DRAMSpec are made public available and a release of DRAMSys is planned for this year. These models require continuous improvements, especially in terms of scaling and new technologies. We have tackled this with a new DRAM measurement infrastructure to calibrate our models with real measurement data. A new address mapping method, the ConGen methodology, and a refresh-aware scheduler were investigated to derive an optimized memory address mapping for specific applications and to reduce the influence of refresh on the system performance accordingly.
Publications
- “A Cross Layer Approach for Efficient Thermal Management in 3D Stacked SoCs”. Journal of Microelectronics Reliability, Elsevier 2015
M. Jung, C. Weis, N. Wehn
(See online at https://doi.org/10.1016/j.microrel.2015.12.025) - “DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework”. IPSJ Transactions on System LSI Design Methodology (T-SLDM), August, 2015
M. Jung, C. Weis, N. Wehn
(See online at https://doi.org/10.2197/ipsjtsldm.8.63) - “Thermal Aspects and High-level Explorations of 3D stacked DRAMs”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2015, Montpellier, France
C. Weis, M. Jung, C. Santos, P. Vivet, O. Naji, A. Hansson, N. Wehn
(See online at https://doi.org/10.1109/ISVLSI.2015.60) - “Approximate Computing with Partially Unreliable Dynamic Random Access Memory: Approximate DRAM”. In Proc. IEEE/ACM Design Automation Conference (DAC), June, 2016, Austin, TX, USA
M. Jung, D. Mathew, C. Weis, N. Wehn
(See online at https://doi.org/10.1145/2897937.2905002) - “DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool (DOI)”. International Journal of Parallel Programming (IJPP), Springer, 2016
C. Weis, A. Mutaal, O. Naji, M. Jung, A. Hansson, N. Wehn
(See online at https://doi.org/10.1007/s10766-016-0473-y) - “A Platform to Analyze DDR3 DRAM’s Power and Retention Time” IEEE Design & Test, 2017
M. Jung, D. Mathew, C. Rheinländer, C. Weis, N. Wehn
(See online at https://doi.org/10.1109/MDAT.2017.2705144) - “Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact”. ACM International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA
R. Jagtap, M. Jung, W. Elsasser, C. Weis, A. Hansson, N. Wehn
(See online at https://doi.org/10.1145/3132402.3132444) - “Using Run-Time Reverse-Engineering to Optimize DRAM Refresh”. ACM International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA (Best Paper Award)
D. M. Mathew, É. F. Zulian, M. Jung, K. Kraft, C. Weis, B. Jacob, N. Wehn
(See online at https://doi.org/10.1145/3132402.3132419) - “An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs”. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany
D. M. Mathew, M. Schultheis, C. C. Rheinländer, C. Sudarshan, M. Jung, C. Weis, N. Wehn
(See online at https://doi.org/10.23919/DATE.2018.8342023)
