Architecture and Compiler of the High-Performance Reconfigurable Processor (HiPReP)

• Applicant: Professor Dr.-Ing. Markus Weinhardt
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems ; Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2016 to 2021
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 283321772

In the area of high-performance computing (HPC) parallel processor architectures (multi- and many-core processors, and Graphics Pocessing Units - GPUs) have been increasingly used in the last few years since no performance increase could be achieved any more by higher clock frequencies. However, these solutions based on many single processor kernels come with a large chip area and a high power consumption. On the other hand, programmable hardware in the form of FPGAs (Field-Programmable Gate Arrays) is also used for HPC applications since FPGAs allow massively parallel processing without the overhead of complete processor kernels. But processing floating-point data as required in most HPC applications is problematic on FPGAs. Only a limited number of floating-point units (FPUs) can be realized on an FPGA by combining simpler components. The same limitation also holds for coarse-grained reconfigurable arrays (CGRAs) which are - as opposed to FPGAs - based on processing units for data words (e.g. 32 bit words). This makes them in principle better suited for executing numerical algorithms. But almost all CGRAs developed so far contain only units for processing integer or fixed-point data. CGRAs extended by FPUs are a promising option for computation-intensive algorithms, e.g. in the domains of scientific computing or 3D graphics. This extension will be researched and evaluated in this proposed three-year project. First, suitable HPC benchmark program kernels will be selected and analyzed. The new CGRA will be optimized for these kernels. In the second work package, the parameterized HiPReP architecture, i.e. the design of the hardware, will be determined and a simulation model in the SystemC language will be implemented. For efficiently using the extension by FPUs, novel communication and synchronization mechanisms have to be devised, and the integration of a HiPReP module in the memory hierarchy of a HPC system must be investigated. A full-time PhD student will mainly work on these two work packages. A second PhD student is planned for implementing a high-level language compiler prototype for HPC applications on HiPReP. This is required since the practical use of a processor can only be evaluated with a corresponding compiler. For this, suitable compilation, scheduling and placement algorithms will be developed. Finally, a design space exploration will be performed in the evaluation phase of the project. Therefore, the benchmark kernel executions will be simulated on the HiPReP processor, and an optimal point in the design space will be determined. For this design, the area, frequency and power consumption of a chip implementation will be estimated.

• DFG Programme: Research Grants