Design-for-Test and Design-for-Reliability for Low Power STT-MRAM
Computer Architecture, Embedded and Massively Parallel Systems
Final Report Abstract
In any computing system, data storage and data movement are crucial steps. Therefore, there are various on-chip and off-chip data storage technologies as well as data movement schemes in order to provide high performance and high storage capacities, while maintaining energy efficiencies. In terms of on-chip storage, multiple levels of caching and storage technologies have been used which provide different flavors of density vs speed. While static random access memories (SRAM) offer better speed, dynamic random access memories (DRAM) provide better density. Therefore, the first levels of cache memories, including the on-core storage such as register files, are designed using SRAM technology and last level caches (LLC) or main memories are designed with DRAM technology. While technology scaling has provided benefits in terms of area reduction and performance improvements, both of these dominant on-chip memory technologies are facing various challenges, making them very hard to scale any further. Additionally, these memories are volatile, meaning that they lose their contents when they are powered off. While the amount of static (aka leakage) energy is increasing for these technologies, power gating strategies are not very straightforward for such memories as they lose their content and the valid data in such memories need to be saved somewhere else before they can be powered off. Due to these challenges, non-volatile memory technologies are very desirable for the replacement of on-chip SRAM and DRAM memories, particularly for normally-off and instanton computing to save leakage energy. Among several emerging non-volatile technologies, sprintronic memories, such as spin transfer torque (STT), have gain lots of interest in both industry and research communities due to several attractive features such as non-volatility, high density, high retention, high endurance and CMOS compatibility. However, there are several reliability and testing issue of this emerging technology which should be resolved, before widespread deployment. While the switching behavior of spintronic memories is inherently stochastic, the variability in the read and write operations of these memories should be modeled and accounted for at the design level. Additionally the source of yield detractions in this technology should be understood and proper yield improvement techniques should be devised. At the same time the manifestation of manufacturing defects in this technology is very different than conventional CMOS-based memories, due to additional magnetic layers. Therefore, proper fault modeling for spintronic memories should be performed and accordingly, specific memory test patterns need to be developed for MRAM memories. The objective of this project was to explore reliability and test challenges in spintronic memories and provide proper models and techniques to analyze the variation effects in this technology, perform yield modeling and design for yield explorations, and finally perform reliability evaluation, design for reliability as well as defect characterization, fault modeling and test pattern generation for STT-MRAM memories.
Publications
- "Design of Defect and Fault Tolerant Non-Volatile Spintronic Flip-Flops", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017
R. Bishnoi, F. Oboril and M.B. Tahoori
(See online at https://doi.org/10.1109/tvlsi.2016.2630315) - "Leveraging Systematic Unidirectional Error-Detecting Codes for Fast STT-MRAM Cache", in proceedings of VLSI Test Symposium (VTS), 2017, USA
N. Sayed, F. Oboril, R. Bishnoi, and M. B. Tahoori
(See online at https://doi.org/10.1109/vts.2017.7928937) - "Opportunistic Write for Fast and Reliable STT-MRAM", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland
N. Sayed, M. Ebrahimi, R. Bishnoi, and M. B. Tahoori
(See online at https://doi.org/10.23919/date.2017.7927049) - "VAET- STT: A Variation Aware Estimator Tool for STT-MRAM based Memories", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland
S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril, and M. B. Tahoori
(See online at https://doi.org/10.23919/date.2017.7927221) - "VAET-STT: A Variation Aware STT-MRAM Analysis and Design Space Exploration Tool", in IEEE Transcactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017
S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril, F. Hameed, and M. B. Tahoori
(See online at https://doi.org/10.1109/tcad.2017.2760861) - "Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM", In Proceedings of International Test Conference (ITC), 2018, USA
S. Mohanachandran Nair, R. Bishnoi, M.B. Tahoori, G. Tshagharyan, H. Grigoryan, and G. Harutyunyan
(See online at https://doi.org/10.1109/test.2018.8624725) - "Parametric Failure Modeling and Yield Analysis for STT-MRAM", in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany
S. Mohanachandran Nair, R. Bishnoi, and M. B. Tahoori
(See online at https://doi.org/10.23919/date.2018.8342016) - "Process Variation and Temperature Aware Adaptive Scrubbing for Retention Failures in STT-MRAM", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018, Korea
N. Sayed, S. Mohanachandran Nair, R. Bishnoi, and M.B. Tahoori
(See online at https://doi.org/10.1109/aspdac.2018.8297306) - "A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019
S. Mohanachandran Nair, R. Bishnoi, M. B. Tahoori
(See online at https://doi.org/10.1109/tvlsi.2019.2904197) - "Fast and Reliable STT-MRAM Using Non-uniform and Adaptive Error Detecting and Correcting Scheme", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019
N. Sayed, R. Bishnoi, and M.B. Tahoori
(See online at https://doi.org/10.1109/tvlsi.2019.2903592) - "Mitigating Read Failures in STT- MRAM", in proceedings of VLSI Test Symposium (VTS), 2020, USA
S. Mohanachandran Nair, R. Bishnoi, and M.B. Tahoori
(See online at https://doi.org/10.1109/vts48691.2020.9107605)
