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FAST - Reliability Assessment using Faster-than-at-Speed Test

Subject Area Computer Architecture, Embedded and Massively Parallel Systems
Term from 2017 to 2023
Project identifier Deutsche Forschungsgemeinschaft (DFG) - Project number 341939202
 
Final Report Year 2023

Final Report Abstract

Nanoscale technologies enable the integration of highly complex systems on a single chip, but also lead to challenges in test and reliability screening. In particular, marginalities can cause early life failures associated with high economical losses. Typically, they cannot yet be observed during manufacturing test or are difficult to distinguish from acceptable parameter variations. Traditional burn-in tests use additional stress to provoke early life failures before shipping products to the customer. The project „Reliability Assessment by Faster-than-at-Speed Test” (FAST) has targeted new test strategies and test infrastructure to identify potential early life failures already during manufacturing test and to support the silicon lifecycle management. Recent trends show that this is of increasing importance when innovative FinFET technologies are used for safety critical applications, as for example in the automotive domain. The developed techniques mainly rely on the circuit delay as a non-functional indicator. The project has shown that tests for small delay faults at varying supply voltages and test frequencies can accurately distinguish between critical defects and benign parameter variations when properly combined with machine learning techniques for data analysis. Further research has focused on “hidden” delay faults which become visible along short paths and can be detected by overclocking the circuit, only. A high fault coverage with a minimum number of test frequencies is achieved by the developed algorithms for frequency selection. However, the number of unpredictable output values (X-values) increases with the test frequency. The developed SAT- based algorithm for automatic test pattern generation (ATPG) therefore works with user-defined observation times and minimizes X-values. For test validation, powerful GPU-simulators at gate and switch level exploit the multi-dimensional parallelism of the simulation process. This way, the statistical analysis of a large number of circuit instances becomes feasible, which provides the basis for the efficient analysis of the circuit under parameter variations. To deal with X-values during BIST, the test response compactor combines an adaptive space compactor with an X-canceling MISR (multiple input signature register). The space compactor can be adjusted to high X-rates and allows to control the trade-off between X-reduction and fault efficiency. This way, the MISR needs less resets and the storage requirements for intermediate signatures are reduced. The basic BIST infrastructure has been extended by programmable delay monitors which can be used for online monitoring as well as during BIST. For system level test, respective techniques for interconnect testing indicate reliability threats caused by electromigration.

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