Delta-Sigma-ADC with dynamic clock control

• Applicant: Professor Dr.-Ing. Dirk Killat
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2017 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 391630368

• Final Report Year: 2022

Final Report Abstract

A continuous-time delta-sigma modulator with switchable clock frequency was realized on a test chip. This is suitable to be used as part of a dynamic delta-sigma ADC. Such ADCs are suitable for self-regulating their clock frequency. The modulator was manufactured in a 65nm CMOS technology. For the digital part of the ADC, the Kintex-7 FPGA on a Genesys 2 FPGA board was used. This novel design has been presented at several conferences in recent years. Further research on dynamic ADCs is possible based on this work. The optimization of the control algorithm is an important point for further investigations. The performance of the developed test chip did not quite meet our expectations, especially at 64/32 MHz, where the SNR is 10-12 dB worse than at the other lower frequencies. A search for the reason of this will keep us busy in the near future, so that this will not occur again in future projects, or we will focus more on this problem. The clock control, on the other hand, has met our expectations after some optimizations and adjustments. Excessive switching has been significantly reduced and the individual control variants behave as expected with the appropriate signals. This part of the work still represents a point where a lot of research can be done. The algorithms can be extended or optimized, realistic signal characteristics can be used for testing and the switching thresholds for switching can be shifted to achieve better switching behavior.

Publications

• “Delta-Sigma-ADC mit dynamischer Taktsteuerung”, 20. Workshop Analogschaltungen 2018, Freiburg, März 2018
  P. Pitonak, D. Killat
  
• “Einfluss der Taktratensteuerung auf die Genauigkeit asynchroner ADCs”, ANALOG 2018, München, September 2018
  P. Pitonak, D. Killat and H. Zhu
  
• "Time-continuous Delta-Sigma-Modulator with switchable resistors in 65 nm CMOS Technology," 2022 3rd URSI Atlantic and Asia Pacific Radio Science Meeting (AT-AP-RASC), 2022, pp. 1-4
  P. Pitonak and D. Killat
  (See online at https://doi.org/10.23919/AT-AP-RASC54737.2022.9814345)