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Aged but Fit: Long Lasting Security for Trusted Platforms

Subject Area Security and Dependability, Operating-, Communication- and Distributed Systems
Computer Architecture, Embedded and Massively Parallel Systems
Term from 2019 to 2022
Project identifier Deutsche Forschungsgemeinschaft (DFG) - Project number 418658052
 
Final Report Year 2023

Final Report Abstract

The main goal of this project was to evaluate the effect of aging on the security of cryptographic devices and also to improve their security characteristics by designing aging-aware countermeasures. This objective is essential; while all cryptographic devices face aging during their usage period, there is a need to conduct coherent research in this area. Many applications, including electronic identification with smart cards or phones for banking, traveling, and access restriction, and security-enabled devices for automotive, medical, smart home, and industrial automation purposes, rely on robust cryptography implemented (primarily) in tiny and cheap pieces of hardware. The cryptographic implementations on such devices not only have to be mathematically secure, they also need to withstand attackers that gain physical access to the hardware and may observe its emissions during the execution of cryptographic protocols. One of the primary sources of unintentional information leakage in such scenarios is computing devices’ static or dynamic power consumption. When adversaries can measure a cryptographic device’s power consumption while processing secret information like cryptographic keys, it is possible to learn information about those secrets through side-channel analysis. Although every countermeasure has been thoroughly evaluated against side-channel analysis before commercial usage, most security evaluations on cryptographic peripherals are done without considering the effect of device aging. It is well known that the main aging-induced effect on CMOS transistors is increasing the device’s threshold voltage. This, in turn, causes an increase in the delay of gates and hence delay of the device in whole. In particular, while modern countermeasures against side-channel analysis strengthen the device’s robustness, in some scenarios, aging can threaten such robustness. Hence, it is required to pay more attention to the effect of aging on the security characteristic of cryptographic devices when evaluating the side-channel security of embedded devices. This project tried to take the first step in that direction by designing and manufacturing a test chip in a 65 nm CMOS technology including several physically-protected cryptographic cores in order to examine their resistance when the device is aged. During this project, we discovered that aging sometimes makes the attacks harder, but in several cases, it can be particularly advantageous from the attacker’s point of view. For instance, in power-equalization countermeasures against side-channel analysis attacks, aging can change the balance between the dual rails, what is essential for such countermeasures. Furthermore, in some active attack scenarios, e.g., fault sensitivity analysis, an increase in the circuit delay originating from device aging makes such attacks easier. It should be noted that adversaries can significantly increase the speed of aging by controlling the environment, where the device is being operated, e.g., by increasing the supply voltage as well as the temperature. This highlights the needs for aging-aware countermeasures. Among several investigations and developments, we developed a solution which is a combination of dual-rail pre-charge logic and masking countermeasure that up to an extent can mitigate the effect of aging on power-equalization countermeasures.

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