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Electronic Analog Multiplexer for High-Speed Communication Systems (ELAMUR)

Subject Area Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Term from 2019 to 2024
Project identifier Deutsche Forschungsgemeinschaft (DFG) - Project number 423436357
 
Final Report Year 2025

Final Report Abstract

The uninterrupted, exponential growth of global data traffic requires ever-higher signal bandwidths on optical transmission links to increase data throughput without the need for additional transmission channels. On the transmitter side, this particularly affects the electronic digital-to-analog converters (DACs). Because of their cost and energy efficiency, high-speed DACs today mainly use CMOS technologies, with current DACs reaching up to 120 GS/s and the latest 3-nm technologies expected to enable up to 200 GS/s in the next few years. However, the very small transistor dimensions and the multilayer, very fine metallization stack required for them impose large parasitic capacitances, severely limiting the analog output bandwidth of CMOS DACs. In contrast, heterostructure bipolar transistors on silicon germanium (SiGe) offer higher cutoff frequencies with much coarser metallization and thus higher signal bandwidth. However, the low level of integration, low power and cost efficiency, and thermal issues prevent the application of SiGe-only DACs in commercial data links. Therefore, hybrid concepts that combine CMOS DACs with less complex SiGe circuits to increase sample rate and bandwidth are promising. The analog multiplexer (AMUX) is one such circuit that can combine multiple DAC outputs into a single output signal to achieve output bandwidths exceeding 100 GHz, a value unattainable for pure CMOS DACs at the current state. During the ELAMUR project, the applicants have designed and fabricated several 2-to-1 SiGe AMUX ICs that achieve an analog bandwidth of over 110 GHz. In terms of the output symbol rate achieved using AMUX, the attained results set the current state of the art, with 190 GBd at 4 signal stages (PAM- 4). This was achieved using an on-chip clock doubler and advanced signal predistortion developed using an extensive simulation framework for 2-to-1 multiplexers. To achieve even higher symbol rates and bandwidths, a larger number of DAC channels must be combined. The applicants have therefore carried out preliminary work for a 4-to-1 AMUX, including schematic simulations for a direct 4-to-1 AMUX IC and the setup of a platform for cascaded N-to-1 multiplexing. The results achieved in this project are the basis for future AMUX designs in SiGe-HBT technology for symbol rates of up to 300 GBd and beyond. The project has thus made a valuable contribution to meeting the ever-increasing demand for data throughput in a sustainable and efficient manner, despite the diminishing advances in CMOS semiconductor technology.

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