NeuroTest: Testing Solutions for Neuromorphic Circuits and Architectures

• Applicant: Professor Mehdi B. Tahoori, Ph.D.
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems ; Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2019 to 2024
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 429238884

Deep neural networks (DNNs) are gaining increasing attention and usage in many fields related to artificial intelligence and cognitive processing. Due to challenges associated with the implementation of DNNs using traditional computing architectures, there is a growing interest for brain-inspired, aka Neuromorphic computing platforms and paradigms for direct and hence more efficient implementation of DNNs. The building blocks and operation mode of circuitries and the architectures for Neuromorphic computing bring new challenges, since the implementation and operation of neural networks is fundamentally different from traditional Boolean logic. From the technology point of view, they are based on emerging non-volatile resistive memories, which have new fabrication processes and steps, and hence subject to new types of defects and failures. At the circuit-level, they use synapses and neurons as the building blocks; which are mostly analog or contain many analog components (to store weights, and process firing functions) so there is no clear distinction between analog and digital components. They may also work on analog inputs, such as spiking inputs, as used in spiking neural networks. The non-volatile resistive memory devices perform both storage and logical operations (aggregation function), so there is no clear separation of memory storage and logic blocks. From the functional perspective, unlike Boolean logic in which correct digital value of all output bits are required during all operational cycles, neural networks have inherent inaccuracy and non-determinism, which means they have intrinsic tolerance to faults. Both training and inference phases are inherently imperfect and contains some errors. Given these fundamental challenges, in technology, circuitry and functionality of neural networks and neuromorphic implementations compared to traditional digital circuits and architectures, it requires fundamentally new approaches in testing, test pattern generation and Design for Test (DfT) requirements and methods for neural networks and Neuromorphic circuits. In the new philosophy of testing as needed for Neuromorphic circuits, the traditional boundaries between digital and analog test, memory and logic test, structural and functional test do not longer exist. The purpose of this proposal is to develop proper fault models, design for test, and test generation schemes for Neuromorphic circuits and architectures to tackle these challenges.

• DFG Programme: Research Grants