Project Details
Projekt
SecuReFET II: Secure Circuits through inherent Reconfigurable FET II
Subject Area
Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Term
since 2020
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 439891087
Security solutions based on classical CMOS electronics are either cost-intensive due to a high area overhead or energy inefficient. One promising option to fight against these hardware-level attacks in the future electronic system is emerging nanotechnologies, such as reconfigurable field effect transistors (RFETs) with programmable p- and n-function. The runtime-reconfigurable nature of those nano-electronic devices yields an inherent polymorphic functionality at the logic gate level. The big difference to standard CMOS electronics is, that the actual circuit or function remains hidden since they cannot be differentiated from other possible combinations by physical reverse engineering or electrical monitoring of the circuit (i.e., by side-channel attacks). In SecuReFET-I gate-level demonstrators with polymorphic functionality have been fabricated and measured. RFET promises in terms of side-channel-resistance and providing deliberate security functions and RFET vulnerabilities have been explored. An RFET-compatible automated design-synthesis environment (EDA) for logic and physical design has been developed. Phase II of the project aims to extend on all of those topics. Firstly, lab demonstrators comprising multiple logic gates connected by an additional metal level will be built and measured. Secondly, a ferroelectric layer will be added to the RFETs to offer non-volatile memory elements directly in the device. Storing the key directly in the logic hinders the potential attack on the interface between memory and logic. Preferably, the function of the transistor can be written directly after processing within the foundry and are not externally accessible later on, potentially solving one of the core questions of hardware security by making the interface between memory and locking circuit unattackable. Further, the unique side-channel resistance features of RFETs providing new opportunities for hardware designers to deliver more effective side-channel attack (SCA) protection with less area and energy overhead will be explored in greater detail. In addition, unlike existing countermeasures that mainly focus on data protection, RFET-based polymorphic cells can also provide the possibility of protecting intellectual property (IP) against SCAs. Thus, the extended exploration of how to harness the RFET features (both in volatile and non-volatile versions) to provide resiliency against timing and power SCAs (from cell to circuit level) for IP and data protection will be studied. Finally, the ferroelectric security and SCA features will be integrated into the EDA synthesis flow developed in SecuReFET-I.
DFG Programme
Priority Programmes
Co-Investigator
Dr.-Ing. Jens Trommer
