Efficient Power Amplifiers for Aggressive Duty-Cycling (EPAAD)

• Applicant: Professor Dr.-Ing. Frank Ellinger
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2020
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 448290433

The energy consumption of future millimetre-wave communications has to be reduced. Peak data rates are only required during a short duration. Artificial intelligence (AI) inspired adaptive duty-cycling providing data packages with duration down to the sub-μs range is very attractive to save energy. The sleep times can be > 10 000 times longer than the active operation times. The latter can be in a similar range or even smaller than the DC operation point switching (OPS) times. Thus, the overall energy consumption is not only determined by the active operation but also by the sleep and OPS states. In transceivers, a major part of the DC power is drawn by the power amplifiers (PAs). A huge number of works were published treating the reduction of the PA energy efficiency in active operation. Until today, much less attention was spent on the minimization of the PA energy consumed during the sleep and OPS states. To pave the way for a new class of ultra-efficient aggressive duty-cycling, EPAAD explores approaches to minimize the OPS and sleep energies. Due to the option to go for ultra-short data bursts at minimum DC overhead, energy can be saved. Class-E PAs are employed to keep also the energy for active operation as low as possible. The OPS times are mainly determined by the time constants associated with the feeding inductance handling the supply current change, control nodes, PA core, LC-impedance matching, RF-ground-shunt and AC-coupling capacitors. To reduce the feeding inductance and the associated time constant, we go for an inverse class-E architecture. Cascode-like transistor stacking reduces the Miller effect and the RC constant of the PA core. A differential topology minimizes the required sizes and delays of the RF-shunt capacitors. To minimize the leakage in sleep mode, the gate voltage of the common source stage has to be pulled down leading to a larger OPS duration. The switching of the upper gates while keeping the lower gate at high level results in lower OPS times. Hence, we investigate novel control schemes with sequential switching of stacked transistors to reduce both the OPS and sleep energies. To verify the approaches, a 28 GHz PA is designed in 22 nm FDSOI CMOS. Globalfoundries offers us non-released transistors targeting a leading-edge figure of merit with drain source breakdown voltage of ≈ 4.2 V while still providing a high maximum frequency of oscillation of ≈ 250 GHz. Key quantitative PA goals are record on/off OPS times < 10 ns, sleep leakage currents < 500 nA, an RF output power > 24 dBm and 40 % power added efficiency (PAE). For this research, DFG funding is requested by Frank Ellinger at TU Dresden. Based on these insights, additional tasks regarding simulation-based energy and performance investigations of full transceivers are performed by Prof. Méndez from Pontificia Universidad Javeriana (PUJ) in Columbia.

• DFG Programme: Research Grants
• International Connection: Colombia
• Cooperation Partner: Professor Diego Méndez Chaves, Ph.D.