Coupled Hybrid Bandwidth Peaking Techniques for BiCMOS Multiplexer and Demultiplexer Beyond 200 Gb/s (PEAK)

• Applicant: Professor Dr.-Ing. Frank Ellinger
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering ; Communication Technology and Networks, High-Frequency Technology and Photonic Systems, Signal Processing and Machine Learning for Information Technology
• Term: since 2021
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 464608440

Communication systems operating beyond 100 Gb/s will be required in the future. To enable such ultra-high data rates, the data can be split in multiple parallel streams with lower speed using multiplexer (MUX) and demultiplexer (DMUX) circuits. In BiCMOS, MUX ICs with data rates up to 180 Gb/s and DMUX ICs up to 100 Gb/s were published. To reach maximum speeds, inductive bandwidth peaking techniques are required. Most frequently, series, shunt or T-coil peaking approaches are applied, which are capable to improve the bandwidth by factors up to 1.4, 1.7 and 2.8, respectively. PEAK wants to push the state of the art of MUX and DMUX in BiCMOS beyond 200 Gb/s. Latches for synchronisation will be included. T-coils are mainly realised using coupled spiral inductors providing self-resonance frequencies (SRFs) well below 200 GHz. Hence, they are not suited for PEAK. We investigate novel transmission-line-based T-coils capable to operate well beyond 200 GHz. T-coil peaking exploits strong mutual coil coupling. However, around 200 GHz, the ratio between the length of the coupled lines and the line distances is low. This leads to smaller coupling factors and hence less efficient peaking. We want to investigate how the coil coupling can be maximised while keeping the SRFs high. Furthermore, we study how ICs with moderate T-coil coupling can be optimised, e.g. by adding of poles and smart combination with series and/or shunt peaking. These higher order peaking methods are extended by smart distribution of heterogeneous peaking approaches at the input, intermediate and output nodes of cascaded circuit blocks. To deeply understand the potentials and limits, equations are derived. In addition to the bandwidth, we investigate also trade-offs with respect to the step response, jitter of the clock and data signals and group delay, to finally allow large eye-openings. The packaging parasitics will be taken into account. Optionally, we investigate also multi-phase architectures to relax the speed of the latches. To verify the approaches, MUX and DMUX demonstrator ICs are realised in the fastest IHP BiCMOS technology. Our preliminary simulations predict that MUX and DMUX speeds beyond 200 Gb/s should be possible. The circuits will be applied for 2 applications: First, as enabler for faster communication systems, and second, to extend our MORE measurement platform, which can be assessed by third party users. MORE includes e.g. our state-of-the-art SHF bit-error-rate-tester (BERT), which is capable to measure circuits up to 120 Gb/s per path even with non-return-to-zero (NRZ) modulation. By applying two paths using the PEAK MUX and DMUX, we can extend the MORE-BERT towards a record speed of 200 Gb/s per path. This will also be beneficial for the MORE partners consisting of 12 chairs from 6 German universities. Hence, PEAK strengthens the German research community to design fastest ICs.

• DFG Programme: Research Grants