Analog High-Frequency Integrated Circuits based on Carbon Nanotube Field-Effect Transistors (ICCNT)

• Applicants: Dr.-Ing. Sascha Hermann; Professor Dr.-Ing. Michael Schröter
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 466828598

By now, carbon nanotube(CNT)- based field-effect transistors (FETs) have emerged as the most competitive successor for bulk material based FET technology. This is due to the advantageous material properties (such as high carrier mobility, high thermal stability) of CNTs as well as their versatile applicability (e.g. in FETs, sensors, flexible electronics). Hence, the long-term vision is the realization of a CNT-based system-on-chip (SoC) with high functionality in the area of analog and digital signal processing in combination with a variety of sensor elements (chemical, mechanical, radiation). Moreover, an important part of such SoCs are high-frequency (HF) circuits for wireless data communication with the external environment. The required HF-CNTFETs have recently demonstrated comparatively high external cut-off frequencies similar to those of silicon MOSFETs of the same technology node, although the CNT density as well as the drain current per CNT are still far below the theoretically possible limits. These recent results demonstrate that the performance of CNTFETs will surpass that of silicon and presently considered III-V semiconductor based HF-MOSFETs in the long run. Within this project truly integrated analog HF circuits as well as HF subsystems based on CNTFETs will be realized and studied for the first time. In particular amplifiers, mixer and oscillators along with receiver and transmitter units will be designed and fabricated on the basis of the 130 nm CMOS technology node. Up to now one major bottleneck for realizing integrated CNTFET circuits was the absence of suitable passive HF components (inductors, capacitors, resistors). Therefore, a heterogeneous integration of our wafer-level CNTFET technology with a commercially available mature Back-End-of-Line (BEOL) will be pursued. The circuit relevant BEOL wirings will be designed within this project. Employing a commercially available BEOL also enables a realistic assessment of the competitiveness of CNTFET based integrated circuits with respective HF-CMOS circuits. The necessary processing steps for combining the CNTFET technology with the BEOL will be developed within in a modular technology concept, which aims at not only the enhancement of CNTFET HF performance and long-term stability but also the reduction of process related inter-device variations. In particular, the implementation of technological measures for reducing parasitic capacitances within the FET structure and the optimization our wafer-level CNT integration process will be addressed. Technology development and circuit design effort will be supported by extensive device simulation and compact modelling as well as electrical and physical device characterization.

• DFG Programme: Research Grants