A Three-Level Converter with Dynamic and Adaptive Common-Mode Voltage Suppression
Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Final Report Abstract
The main objective of this project was to investigate the origins of common-mode voltage (CMV) noises in SiC MOSFET-based three-level T-type inverters (3LTTI) used in motor drive systems and propose methods for their mitigation. This project specifically aimed to answer the question: "Is full CMV suppression practically possible?" Therefore, this project analyzed the voltage dynamics of SiC MOSFET-based inverters, focusing on both turn-off and turn-on processes. For the turn-off process, two scenarios were considered. In high load current scenarios, the linearized MOSFET model accurately predicted voltage transition times by considering the behavior of the channel current and the dynamic characteristics of parasitic capacitances. In low load current scenarios, a simplified analytical expression based on the charging of output capacitances provided a practical approximation, as the linearized MOSFET model was ineffective since the channel current fell to zero at the end of the Miller plateau. Voltage transition times of turn-off process varied significantly with load current, decreasing as the load current increased. For the turn-on process, the linearized MOSFET model provided accurate predictions of voltage transition times, which were relatively stable across different load currents. Although achieving zero CMV is theoretically unattainable in a two-level voltage source inverter (2L-VSI), it can be realized in a 3LTTI by selecting specific switching states. However, the necessary simultaneous switching of two half-bridges in zero CMV methods generates significant CMV noises due to dead-time and differences in output voltage transition times. This project proposed methods to mitigate these CMV noises through deadtime and edge-time compensations, which involve precisely adjusting the timing of transitions in the gate drive signals. Results indicate that dead-time compensation can significantly reduce CMV within a frequency range of up to 1 MHz. Furthermore, integrating edge-time compensation with dead-time compensation results in additional CMV reduction up to 1 MHz. The investigation revealed that due to the ringing effect and variable rise and fall times of inverter output voltages, achieving zero CMV is practically unachievable. The findings show that using the zero CMV technique with dead-time and edge-time compensation yields similar results to active EMI filtering methods, where low-frequency EMI noises are effectively reduced, but challenges remain in mitigating high-frequency (HF) noises. The significant reduction in low-frequency noise minimizes the required size of passive filters.
Publications
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“Common-mode emi noise modeling of three-level t-type inverter for adjustable speed drive systems,” in 2022 24th European Conference on Power Electronics and Applications (EPE’22 ECCE Europe), IEEE, 2022, pp. 1–8.
V. Karakasli, A. Allioua & G. Griepentrog
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Common-Mode Voltage in Three-Level T-Type Inverter: Modeling, Analysis, and Compensation. 2024 IEEE Applied Power Electronics Conference and Exposition (APEC), 2586-2593. IEEE.
Karakaşlı, Vefa; Jamal, Adeel; Griepentrog, Gerd & Safdarzadeh, Omid
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“Online measurement of rise and fall times in SiC MOSFET- based inverter output voltage,” in Energy Conversion Congress and Exposition (ECCE) Europe 2024, IEEE
V. Karakasli, A. Jamal & G. Griepentrog
