Verfahren zur ausfallsicheren Verdrahtung von Signalnetzen in integrierten Schaltungen

• Applicant: Professor Dr.-Ing. Erich Barke
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2007 to 2011
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 47305300

• Final Report Year: 2011

Final Report Abstract

No abstract available

Publications

• Erhöhung der Ausbeute durch robuste Verdrahtungsnetzwerke. In 1. GMM/GI/GI-Fachtagung Zuverlässigkeit und Entwurf, pages pp. 117-123, 2007
  P. Panitz, A. Quiring, H.-C. Müller, M. Olbrich, E. Barke, and J. Koehl
  
• Robust wiring networks for DfY considering timing constraints. In Proc. of the ACM Great Lakes Symposium on VLSI, pages pp. 43-48, 2007
  P. Panitz, M. Olbrich, J. Koehl, and E. Barke
  
• Considering possible opens in non-tree topology wire delay calculation. In Proc. of the ACM Great Lakes Symposium on VLSI, 2008
  P. Panitz, M. Olbrich, E. Barke, M. Buehler, and J. Koehl