A Universal Framework for Reliable Computing-in-Memory based on Emerging Non-volatile Memories (CIMware)

• Applicant: Professor Mehdi B. Tahoori, Ph.D.
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: since 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 502196634

Computing-in-Memory (CIM) is an emerging paradigm that tightly integrates memory and processing units to minimize the time and energy required for data movement across digital architectures. Among various emerging device technologies, non-volatile memory (NVM) technologies—such as spin-transfer torque (STT) MRAM, resistive RAM (ReRAM), and phase-change memory (PCM)—are particularly promising for CIM implementations. These memristive and spintronic devices serve as both storage and computing units, enabling increased system complexity and performance while significantly reducing power consumption. Consequently, they offer the scientific community a unique opportunity to overcome the limitations of conventional architectures and drive innovation in nextgeneration computing systems. Despite the growing interest in CIM, several fundamental challenges remain open. The architectural design of CIM systems and their integration within memory hierarchies are still active research areas. Additionally, while inmemory computing architectures built on emerging NVM technologies show great promise, many issues related to device maturity, reliability, and dual-purpose functionality (storage + computation) need to be addressed. Unlike conventional CMOS technology—which has benefited from over five decades of optimization—these emerging devices suffer from inherent stochasticity and process variations, making it difficult to meet the stringent reliability requirements of modern computing systems. Furthermore, uncertainties in device reliability can negatively impact system performance and cost, demanding new approaches to CIM-based computing at higher abstraction levels. This project aims to bridge the gap between technology-level advancements in emerging NVMs and architecturelevel design exploration for reliable and energy-efficient CIM systems. Specifically, we will develop a library of reliable and energy-efficient CIM circuit primitives based on various memristive and spintronic technologies. This will serve two key objectives: 1- Enabling practical CIM architectures by developing an NVM-CIM memory compiler at the hardware level and an Application Programming Interface (API) for CIM-enabled architectures at the software level. 2- Providing accurate technology-aware architectural models to benchmark and evaluate the potential of different NVM technologies (MRAM, PCM, ReRAM) for CIM architectures. By developing these technologyaware models and architectural insights, this project will pave the way for further advancements in software, compiler design, and CIM system-level exploration, ultimately accelerating the adoption of energy-efficient and reliable CIM computing paradigms.

• DFG Programme: Priority Programmes
• Subproject of: SPP 2377: Disruptive Main-Memory Technologies