Enabling an Electromigration-Robust Design of Integrated Circuits in Future Technologies

• Applicant: Professor Dr.-Ing. Jens Lienig
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2023
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 525041614

Electromigration (EM) is a critical reliability issue that reduces the time to failure of integrated circuits (ICs). Hence, checking current-density overshoots and associated EM problems is part of the final verification (sign-off) of electronic circuit layouts in state-of-the-art design flows. Two major problems arise from this established EM-sign-off process when designing nano-scale ICs: First, the rising EM susceptibility of metal interconnects in small technologies leads to an increasing number of violations detected during the verification step. Currently applied post-layout repair strategies result in a growing amount of rework that must be done in order to achieve an EM-robust design. Second, the definition of global current density boundaries is not sufficient anymore to capture the complex EM failure mechanisms in nano-scale designs. Here, novel physics-based models are required that are based on the calculation of hydrostatic stress evolution. These stress-related models are highly dependent on the interconnect geometry which must therefore be taken into account in an EM consideration. This project aims to solve these growing reliability problems by adding EM-specific design rules to the layout synthesis: Instead of repairing EM problems after the layout has been created, we suggest incorporating an EM-specific “design rule set” into the routing engine to avoid EM problems to be generated in the first place. EM-specific requirements will thus proactively be taken into account during the design stage, largely eliminating post-layout repairs. These “design rules” can also be applied for the verification of the layouts’ EM robustness and thus be used for EM verification with the standard DRC tool. Hence, in addition to a more reliable layout synthesis, this new methodology also supports an effective and localized EM verification. Overall, our suggested paradigm change from a post-layout repair strategy to a proactive, pre-layout EM consideration will significantly ease the expected increase in EM faults in future nano-scale technologies. The result will be an “add-on” methodology to traditional CAD tools that (1) newly considers EM effects already at the design phase (instead of relying on post-design, verification-based repair steps) and (2) utilizes a novel stress-based EM model (rather than the conventional current-density model). This paradigm shift in the consideration of EM during physical design should enable (1) to scale back today's necessarily large safety factors for layout design and (2) to maximize the applied current-density boundary values (which have been global values up to now) based on the actual local layout configuration.

• DFG Programme: Research Grants