TRR 89:  Invasive Computing

• Subject Area: Computer Science, Systems and Electrical Engineering
• Term: from 2010 to 2022
• Website: Homepage
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 146371743

Invasive computing denotes a novel paradigm for the design and programming of future parallel computing systems. Its unique characteristic is to give a programmer explicit handles to specify and argue about resource requirements in different phases of program execution: Using an invade command, an application may request for a set of processor, memory and communication resources for a subsequent -by default exclusive- usage. In an infect phase, the program is executed in parallel on the obtained claim of resources. A retreat command finally releases the claimed resources again. To support this idea of resource-aware programming, novel language, compiler, and operating system concepts, but also novel architectural aspects in the design of multicore systems had to be investigated and developed from scratch.Mission I: Basic Principles and Invasive Efficiency. As major results of the 1st funding phase, substantial gains in multicore utilisation and efficiency have been shown to be achievable by only claiming resources when necessary and retreating from them if not needed.Mission II: *-Predictability. A unique jewel of invasive computing is the inherent capability to isolate applications from each other by not sharing resources. This feature has shown to enable *-predictability of non-functional qualities of program execution such as execution time, throughput, but also safety and security properties. Current multicore platforms offer little if no support for spatial and/or temporal isolation on demand of an application program. Mission III: Beating Run-Time Uncertainties and Run-Time Requirement Enforcement. Unfortunately, not only the interferences caused when sharing resources such as caches, processors and communication links as being the practice today, makes the analysis of non-functional properties hard. The bounds themselves or their variability might be much too large for any practical use. Yet, isolation alone does not help to reduce the remaining uncertainty caused by input (problem size), environment (e.g. temperature), and machine state (e.g., cache, power manager, etc.). Our goal of the 3rd phase is therefore to close this missing link for making multicore systems available to be used for the billion dollar market of embedded and cyber-physical IoT products where application programs require the strict or at least a loose enforcement of tight non-functional property ranges. Here, through the static analysis of robustness and the automatic generation of verifiable run-time requirement enforcer (RRE) modules (additional code that either locally or globally observes and controls the satisfaction of requirements within prescribed corridors) in combination with run-time requirement monitoring (RRM), we expect to provide the missing link to successfully combine resource awareness and tight predictability of non-functional aspects of program execution on multicore platforms.

• DFG Programme: CRC/Transregios

Completed projects

• A01 - Basics of Invasive Computing (Project Heads Snelting, Gregor ;  Teich, Jürgen ;  Wildermann, Stefan )
• A03 - Scheduling and Load Balancing (Project Head Sanders, Peter )
• A04 - Characterisation and Analysis of Invasive Algorithmic Patterns (Project Heads Bader, Michael ;  Glaß, Michael ;  Wildermann, Stefan )
• A05 - Scheduling Invasive Multi-Core Programs Under Uncertainty (Project Head Megow, Nicole )
• B01 - Adaptive Application-Specific Invasive Micro-Architectures (Project Heads Bauer, Lars ;  Becker, Jürgen ;  Henkel, Jörg ;  Hübner, Michael )
• B02 - Invasive Tightly-Coupled Processor Arrays (Project Head Teich, Jürgen )
• B03 - Power-Efficient Invasive Loosely-Coupled MPSoCs (Project Heads Henkel, Jörg ;  Herkersdorf, Andreas )
• B04 - Generation of Distributed Monitors and Run-time Verification of Invasive Applications (Project Heads Müller-Gritschneder, Daniel ;  Schlichtmann, Ulf ;  Schmitt-Landsiedel, Doris )
• B05 - Invasive NoCs & Memory Hierarchies for Run-time Adaptive MPSoCs (Project Heads Becker, Jürgen ;  Herkersdorf, Andreas ;  Teich, Jürgen )
• C01 - Invasive Run-Time Support System (iRTSS) (Project Heads Bauer, Lars ;  Henkel, Jörg ;  Hönig, Timo ;  Lohmann, Daniel ;  Schröder-Preikschat, Wolfgang )
• C02 - Simulative Design Space Exploration (Project Heads Gerndt, Michael ;  Hannig, Frank ;  Herkersdorf, Andreas ;  Weidendorfer, Josef )
• C03 - Compilation and Code Generation for Invasive Programs (Project Heads Snelting, Gregor ;  Teich, Jürgen )
• C05 - Security in Invasive Computing Systems (Project Heads Freiling, Felix ;  Schröder-Preikschat, Wolfgang ;  Snelting, Gregor )
• D01 - Invasive Software-Hardware Architectures for Robotics (Project Heads Asfour, Tamim ;  Dillmann, Rüdiger ;  Stechele, Walter )
• D03 - Invasive Computing and HPC (Project Heads Bader, Michael ;  Bungartz, Hans-Joachim ;  Gerndt, Michael )
• T01 - TCPA_INT – Integration and Coupling of Tightly Coupled Processor Arrays (Project Heads Hannig, Frank ;  Teich, Jürgen )
• Z - Central Services of the CRC/Transregio and Public Relations (Project Head Teich, Jürgen )
• Z02 - Validation and Demonstrator (Project Heads Becker, Jürgen ;  Hannig, Frank ;  Wild, Thomas )

• Applicant Institution: Friedrich-Alexander-Universität Erlangen-Nürnberg
• Co-Applicant Institution: Karlsruher Institut für Technologie; Technische Universität München (TUM)
• Participating University: Universität Bremen
• Spokesperson: Professor Dr.-Ing. Jürgen Teich