Entwurf von adaptierbaren Prozessoren anhand Erweiterungen statischerKompilierungstechniken durch dynamische Rekonfiguration.
Zusammenfassung der Projektergebnisse
The two main hurdles in the design of application-specific processing elements are: (1) the time-to-market involved in the development of the new micro-architecture and (2) the application mapping process that needs to be modified for every new architecture under consideration. Both these factors make a major impact on the competitive edge for the success of a new product. In this research, firstly, the delay involved in designing a processor that is customised to application-specific needs is circumvented by building a processor-centric adaptable computation fabric. This fabric is available off-the-shelf and can be customised to application-specific computational demands during product deployment. The computational fabric has been optimised for performance and resource-efficiency. Secondly, the tedious overhead of using hardware description languages for the design of application-specific accelerators is eliminated by the use of a software design flow, with standard C-based application description. An application that uses the conventional software design flow simplifies the application-to-target mapping process: a simple compilation scheme translates the functionality to an executable that can be run on any processor. Overall, we present a scheme to design an adaptable, resource-efficient and easy-to-use computational fabric that can be deployed in a wide range of industrial applications. For the computational fabric, we deploy multi-issue soft processors that have proven to be commercially successful in accelerating computationally complex applications. Dedicated accelerators can be coupled to this existing soft processor through the use of additional instruction slots. More particularly, application-specific parallelism can be exposed by using a configurable multi-issue VLIW processor. However, mapping a soft multi-issue processor on an existing reconfigurable fabric proves to be very expensive in terms of performance and area requirement. We introduce processor-centric features in the existing FPGA fabric that result in significant reduction of area and power consumed by the multi-issue soft processor, as compared to the implementation on existing programmable fabrics. To further enhance performance, the existing programmable fabric is augmented with dedicated hard elements that appear frequently in soft processors. As a proof-of-concept, we choose to isolate multiplexers to enhance performance and resource efficiency of soft processors. As a consequence, to accommodate both programmable and non-programmable elements in a single design flow, a heterogeneous technology-mapping scheme has been presented. A diverse set of applications have been mapped on to the new computational fabric, using the heterogeneous technology-mapping scheme. On an average, the applications occupy 16% less area and show a speed up of up to 8%. Further inspired by this scheme, we explore the idea of designing a minimalistic programmable logic element: called the frugal FPGA. Using data analysis on a wide range of benchmarks, we identify a minimal set of functions that are frequently found across applications. These functions are introduced as hard elements alongside programmable logic blocks. Since these hard elements are non-programmable, they are at least 3× faster and occupy at least 10× less area, compared to existing programmable logic blocks. Overall, the three schemes presented aim at reducing design time, enhancing performance and optimising resource efficiency in designing application-specific processors.
Projektbezogene Publikationen (Auswahl)
- Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. FCCM 2012: 224-231
G. Falcao, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
- A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM 2013: 53-56
Madhura Purnaprajna, Paolo Ienne
- Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact. FPGA 2013: 279
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
- Shadow And-Inverter Cones. FPL 2013: 1-4
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
- Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Transactions on Embedded Computing Systems (TECS), Volume 14 Issue 2, March 2015
Muhsen Owaida, Gabriel Falcao, Joao Andrade, Christos Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
(Siehe online unter https://doi.org/10.1145/2656207)
