Designing adaptable processors by extending static compilation techniques with dynamic architectural reconfiguration.

• Applicant: Dr.-Ing. Madhura Purnaprajna
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2010 to 2013
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 181562711

Designing a processor specifically for a given application typically involves two distinct phases. The first phase identifies the computationally intensive parts of the application to determine the building blocks of the processor. In the next phase, the application’s functionality is realised through compilation. As each application has its own diverse computational demands and performance requirements, variations in both these phases are to be expected depending on the type of application executed. Consequently, adaptability according to application-specific requirements is essential in both these phases of the design cycle. This two-phase adaptability is typically absent in present day methodologies. More often the processor architecture has a fixed composition and uses static compilation techniques. We propose a dynamically adaptable architecture that is steered by a customisable compilation flow. The entire process is application-driven, where static compilation techniques are extended with dynamic architectural reconfiguration. A run-time feedback mechanism introduces modifications to the architecture and the compilation process.

• DFG Programme: Research Fellowships
• International Connection: Switzerland
• Host: Professor Dr. Paolo Ienne