Detailseite
Projekt
Runtime reconfigurable analog circuits and adaptive filter synthesis for compensation of unreliable hardware constraints
Antragsteller
Dr.-Ing. Joachim Becker
Fachliche Zuordnung
Rechnerarchitektur, eingebettete und massiv parallele Systeme
Förderung
Förderung von 2010 bis 2014
Projektkennung
Deutsche Forschungsgemeinschaft (DFG) - Projektnummer 182044191
The ongoing downscaling of CMOS processes is dominated by the demands of digital circuits, since memories and high-performance CPUs are the driving forces of VLSI. While transistor scaling has enabled improvements in speed and power-efficiency, it has also introduced various new sources of process variation and device degradation to deep submicron technologies. The first phase of the PP 1500 showed that various hardware-imposed effects in digital circuits are propagated to the logic-level as transient bit-flip faults. Thus, they can be handled either at higher digital hardware levels or even in software, which is covered by many ongoing projects. However, investigation of deep submicron effects on analog circuits showed that these introduce a new class of faults into analog circuit design: In addition to considerably higher mismatch of analog parameters during manufacturing, there are now also degradation effects to be considered, which cause continuous degradation during runtime of the system up to permanent destruction of the functionality. The traditional analog design approach to overcome these problems was overdesign, which in many cases countervails the benefits of technology scaling. Embedded systems commonly require sensor interfaces that utilize analog-to-digital converters (ADCs), which in turn include sensitive analog parts. Overdesign of these circuits for yield and reliability may exceed the digital part in terms of power- and area-consumption, which is undesirable for peripheral parts of embedded systems. Thus, the applicant investigates another approach to resilience of analog circuits during the first phase of PP 1500, which introduces digital monitoring and control of a reconfigurable analog part. Due to a novel approach to structurally reconfigurable analog filters with only little performance tradeoff against dedicated ASICs, it is possible to omit overdesign for reliability. Instead, imperfections of the analog part are taken into account, and compensation of these imperfections is shifted to the digital domain, where – due to downscaling – ever more computation power is available. While the first phase of PP 1500 was used to further improve the reconfigurable analog filter, it is now possible in the second phase, to include it into a self-contained resilient ADC for use in mixed-signal SOCs. The research focus is the digital assistance circuitry, which will be implementing performance measures of the analog part as well as optimization algorithms to allow online monitoring and optimization of the analog performance through runtime reconfiguration of the ADC frontend filter. A communication interface to the assistance circuitry will enable interaction with all hierarchy-levels of the embedded system. Both, runtime changes of analog parameters can be broadcasted, as well as performance constraints can be received, in order to adjust to overall system requirements.
DFG-Verfahren
Schwerpunktprogramme
