Analyse und Entwurf von integrierter CMOS Hochvoltelektronik in Niedervolttechnologien
Zusammenfassung der Projektergebnisse
Until September 2013 the fundamental and basic circuit workpackages of AP 1, AP 2, AP 3 and AP4 were worked on and have been described in the preliminary report. Practical applications were then designed in AP 5. Circuits and partially layouts were prepared to simulate and thus verify the circuit concepts, as well as to manufacture a chip in order to validate the practical usability. Within the project, we could - derive equation based design approaches for HV circuitry in LV CMOS - develop design wrappers to generate safe operating area checks in any technology design kit - derive sub-circuits with the capability of working on elevated higher supply voltages in a modern 65nm low voltage CMOS technology - successfully implement circuits mostly for power management applications.
Projektbezogene Publikationen (Auswahl)
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“An efficiencyenhanced asynchronous buck converter with threshold compensated freewheeling diode”, in 2013 IEEE ISCDG, Sep. 2013
H. Xu, S. Pashmineh, Y. Zhang, D. Killat, and M. Ortmanns
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“An LDO using stacked transistors on 65 nm CMOS”, 21st European Conference on Circuit Theory and Design (ECCTD), September 2013
S. Pashmineh, St. Bramburger, H. Xu, M. Ortmanns, D. Killat
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“Design of high speed HV- drivers based on stacked standard CMOS for various supply voltages”, IEEE MWSCAS, August 2013
S. Pashmineh, H. Xu, M. Ortmanns, D. Killat
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“Technique for reducing on-resistance of highvoltage drivers based on stacked standard CMOS”, 9th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME) 2013, June 2013
S. Pashmineh, H. Xu, D. Killat
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A Wide-Band Efficiency- Enhanced CMOS Rectifier, IEEE ISCAS, 2014
H. Xu, M. Lorenz, U. Bihr, J. Anders, M. Ortmanns
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“Design of a High-Voltage Differential Amplifier Based on Stacked Low-Voltage Standard CMOS with Different Input Stages”, IEEE MIPRO, May 2015
S. Pashmineh, D. Killat
