Entwurf und Charakterisierung von Grundkomponenten für Datenraten bis 160 Gbit/s in 013 µm SiGe:C Heterobipolartechnologie

• Antragsteller: Professor Dr.-Ing. Andreas Thiede
• Fachliche Zuordnung: Elektronische Halbleiter, Bauelemente und Schaltungen, Integrierte Systeme, Sensorik, Theoretische Elektrotechnik
• Förderung: Förderung von 2012 bis 2017
• Projektkennung: Deutsche Forschungsgemeinschaft (DFG) - Projektnummer 219211669

• Erstellungsjahr: 2017

Zusammenfassung der Projektergebnisse

In the first project phase, basic circuit blocks such as 160 GHz VCO >160 GHz dynamic divider by 2, and >80 GHz static divider by 2 have been developed. In the second project phase, these basic circuit blocks together with new circuitry, namely a phase comparator and filter, have been integrated into a PLL. Furthermore, 2:1 multiplexer blocks have been developed and finally integrated into a 4:1 multiplexer, firstly with external clocking, secondly with internal clocking by the PLL and, as a very last experiment, with external clocking and an additional phase shifter.

Projektbezogene Publikationen (Auswahl)

• A Millimeter Wave Quad-Phase Ring Oscillator using 0.13 μm SiGe BiCMOS HBT Technology, International Semiconductor Conf. Dresden-Grenoble, Dresden, 2013
  U. Ali, A. Thiede
  
• 100-166 GHz Wide Band High Speed Digital Dynamic Frequency Divider Design in 0.13 μm SiGe BiCMOS Technology, European Microwave Integrated Circuits Conf., Paris/France, Sept. 2015, pp.73-76
  U. Ali, M. Bober, A. Thiede, S. Wagner
  (Siehe online unter https://doi.org/10.1109/EuMIC.2015.7345071)
• High Speed Static Frequency Divider Design with 111.6 GHz Self-Oscillation Frequency (SOF) in 0.13 μm SiGe BiCMOS Technology, German Microwave Conf., Nuremberg, 2015, pp.241-243
  U. Ali, A. Awny, M. Bober, G. Fischer, A. Thiede
  (Siehe online unter https://doi.org/10.1109/GEMIC.2015.7107798)
• Low Power Fundamental VCO Design in D-band Using 0.13 μm SiGe BiCMOS Technology, German Microwave Conf., Nuremberg, 2015, pp.359-362
  U. Ali, G. Fischer, A. Thiede
  (Siehe online unter https://doi.org/10.1109/GEMIC.2015.7107827)
• An Integrated 118.4 to122 GHz Low Noise Phase Locked Loop (PLL) in 0.13 μm SiGe BiCMOS, Technology German Microwave Conf., Bochum, 2016, pp.282-285
  U. Ali, M. Bober, A. Thiede
  (Siehe online unter https://doi.org/10.1109/GEMIC.2016.7461611)
• Design of Voltage Controlled Oscillators (VCOs) in D-Band and their Phase Noise Measurements using Frequency Down-Conversion, European Microwave Integrated Circuits Conf., London/GB, Okt. 2016, pp.317-320
  U. Ali, M. Bober, A. Thiede
  (Siehe online unter https://doi.org/10.1109/EuMIC.2016.7777554)