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Design and Characterisation of Basic Components for 160 Gbit/s Data Rate in 0.13 µm SiGe:C Hetero Bipolar Technology

Subject Area Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Term from 2012 to 2017
Project identifier Deutsche Forschungsgemeinschaft (DFG) - Project number 219211669
 
Final Report Year 2017

Final Report Abstract

In the first project phase, basic circuit blocks such as 160 GHz VCO >160 GHz dynamic divider by 2, and >80 GHz static divider by 2 have been developed. In the second project phase, these basic circuit blocks together with new circuitry, namely a phase comparator and filter, have been integrated into a PLL. Furthermore, 2:1 multiplexer blocks have been developed and finally integrated into a 4:1 multiplexer, firstly with external clocking, secondly with internal clocking by the PLL and, as a very last experiment, with external clocking and an additional phase shifter.

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