Sicherheit (Safety) und Verfügbarkeit
Zusammenfassung der Projektergebnisse
The objective of B3 was to ensure safety and availability properties in a system with potentially concurrent changes of multiple components throughout its lifetime. The investigations in the first project phase made clear that automating essential steps of failure analysis is key to reach this goal. A model and a corresponding dependency analysis were developed as a basis. The second phase focused on concrete analysis detecting threats for data integrity, determining timing interference and quantifying reliability and availability. The method allows to automatically attribute technical safety requirements to timing parameters based on a single requirement specified for a component, disburdening also developers in conventional design processes. In designs where verification or further qualification according to the assigned technical safety requirements is impossible, an efficient method to structure a monitoring and enforcement network has been devised. Furthermore, in B3 an availability management method was defined and implemented based on a dedicated hardware fault model for an example reconfigurable FPGA platform, which allows to predict the in-operation reliability figures of hardware and software tasks and allows for optimization of performance and reliability under hanging environment conditions. A hardware monitoring component has been established for error detection and reaction. It was showed on the D1 demonstrator (led by C1) that prediction of the reliability under changing environment conditions and triggering timely reconfigurations for safety critical applications can lead to a more economic resource usage, while availability and reliability constraints are guaranteed. The basic mechanisms are already exploited into actual space projects (e.g. Solar Orbiter PHI DPU). The mechanisms developed in B3 are integrated into the overarching MCC middleware developed in A1, which performs the composition and synthesis based on a contract description of the applications and primitives.
Projektbezogene Publikationen (Auswahl)
- Dependable Reconfigurable Space Systems: Challenges, New Trends and Case Studies. IEEE 20th International On-Line Testing Symposium (IOLTS). Platja d'Aro, Spain, 2014
Antonis Paschalis, Harald Michalik, Nektarios Kranitis, Celia López-Ongil, Pedro Revirie-go Vasallo
(Siehe online unter https://doi.org/10.1109/IOLTS.2014.6873703) - "Cross-Layer Dependency Analysis for Safety-Critical Systems Design" in ARCS Architecture of Computing Systems. Proceedings, 2015 - The 28th International Conference on, 2015
M. Möstl and Rolf Ernst
- Integration of SRAM-FPGas for Hardware Acceleration of a Data Processing Module for Space Instruments, PhD Thesis EITP Faculty TUBS, 2017
Holger Michel
- Self-awareness in autonomous automotive systems. Proc. of the Conference on Design, Automation and Test in Europe (DATE), Lausanne, Switzerland, March 2017
J. Schlatow, M. Möstl, R. Ernst, M. Nolte, I. Jatzkowski, M. Maurer, C. Herber, and A. Herkersdorf
(Siehe online unter https://doi.org/10.23919/DATE.2017.7927145) - SEU fault classification by fault injection for an FPGA in the space instrument SOPHI. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Pasadena, CA, USA, Aug. 2017
H. Michel, H. Guzmán-Miranda, A. Dörflinger, H. Michalik und M. A. Echanove
(Siehe online unter https://doi.org/10.1109/AHS.2017.8046353) - Towards model-based integration of component-based automotive software systems. Annual Conference of the IEEE Industrial Electronics Society (IECON17), Beijing, China, October 2017
J. Schlatow, M. Nolte, M. Möstl, I. Jatzkowski, R. Ernst, and M. Maurer
(Siehe online unter https://doi.org/10.1109/IECON.2017.8217479) - Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration. Architecture of Computing Systems (ARCS), Braunschweig, Germany, Apr. 2018
A. Dörflinger, M. Albers, B. Fiethe und H. Michalik
(Siehe online unter https://doi.org/10.1007/978-3-319-77610-1_21) - Platform-centric self-awareness as a key enabler for controlling changes. Proc. of the IEEE, vol. 106, no. 9, pp. 1543-1567, September 2018
M. Möstl, J. Schlatow, R. Ernst, N. Dutt, A. Nassar, A. Rahmani, F. Kurdahi, T. Wild, A. Sadighi, and A. Herkersdorf
(Siehe online unter https://doi.org/10.1109/JPROC.2018.2858023) - Synthesis of Monitors for Networked Systems With Heterogeneous Safety Requirements. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, No. 11, pp. 2824-2834, November 2018
M. Möstl, J. Schlatow, and R. Ernst
(Siehe online unter https://doi.org/10.1109/TCAD.2018.2862458) - Analysis and Enhancement of a Fault-Tolerant NoC for SRAM-based FPGAs in Space Applications. PhD Thesis EITP Faculty TUBS, 2019
Frank Bubenhagen
(Siehe online unter https://doi.org/10.24355/dbbs.084-202001231034-0) - Controlling Concurrent Change - A Multiview Approach Toward Updatable Vehicle Automation Systems. Workshop on Autonomous Systems Design (ASD 2019) (Selma Saidi and Rolf Ernst and Dirk Ziegenbein, Ed.), vol. 68 of series OpenAccess Series in Informatics (OASIcs), Florence, Italy, March 2019
M. Möstl, M. Nolte, J. Schlatow, and R. Ernst
(Siehe online unter https://doi.org/10.4230/OASIcs.ASD.2019.4) - Self-Adaptation for Availability in CPU-FPGA Systems under Soft Errors. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Colchester, UK, Jul. 2019
M. Möstl, A. Dörflinger, M. Albers, H. Michalik und R. Ernst
(Siehe online unter https://doi.org/10.1109/AHS.2019.000-6)
