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End2End100

Subject Area Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Term from 2013 to 2018
Project identifier Deutsche Forschungsgemeinschaft (DFG) - Project number 244576616
 
It is extremely challenging for all protocol layers to come even close to an end-to-end lOOGb/s wireless data rate. Such data rates are only achievable with current technology when parallel processing is intensively utilized on all communication layers. In the End2End100 project we will therefore design novel high performance protocols for the LLC/MAC-layer and the PHY-layer, respectively. Parallelized LLC/MAC protocols will control a multitude of lower data rate PHY channels In (soft) real time to achieve the desired data rate. We will design and implement a suitable NIC-integrated parallel processing platform for these protocols. This platform will be prototyped by means of a commercially available many-core processor to validate our approach and demonstrate that an end-to-end lOOGbit/s data rate with a low error rate can be achieved in practice.
DFG Programme Research Grants
 
 

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