Highest-Linearity Nyquist Rate SAR ADCs in nm-CMOS - NanoSAR

• Applicant: Professor Dr.-Ing. Maurits Ortmanns
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2014 to 2021
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 245868713

Nyquist-rate analog-to-digital converters (ADCs) with high resolution are needed for multiplexed operation in sensor readouts and medical applications, where for tasks such as digital lock-in detection highest linearity is of prime importance. While SAR ADCs are well known for their superior power efficiency in nanoscaled CMOS technology, they show limited effective resolutions and linearity unless techniques are used (oversampling, noise-shaping, etc) which again prevent Nyquist-rate, memoryless operation. The state of the art in high-resolution ADC design is thus dominated by oversampled converters, and for Nyquist-rate operation a significant power penalty has to be paid. In the first phase of this project proposal, a new architecture was investigated which combined an intrinsically linear sigma-delta (SD) DAC into a SAR ADC in order to omit huge capacitive DACs (CDAC) with good matching; for Nyquist rate operation the SD DAC was operated in incremental fashion. A preferred implementation was then investigated, were the DAC is functionally split into a coarse CDAC, serving also as sampling capacitor, and an intrinsically linear incremental SD (I-SD) DAC for the fine conversion steps. The outcome was a SAR ADC in 40nm CMOS, which achieved the highest ever reported linearity while achieving superior power efficiency on the smallest reported area for such resolution. In the second project phase, the motivating goal is to establish further improvements on architectural level, in order to enable the I-SD DAC enhanced SAR ADC to operate at much higher speed. Therefore, the splitting of the coarse CDAC and fine I-SD DAC is further analysed, and it is also evaluated if the I-SD DAC can be ultimately used as calibration engine only; alternatively, much faster operating speed of the I-SD DAC is analysed.Moreover, the new hybrid comparator based on an eye-opening, VCO-structure is enhanced both by modelling its phase noise as equivalent input referred amplitude noise of the comparator, and secondly by investigating, if multibit operation can be used by extracting the phase difference in multivalued rather than binary fashion. Since the new architectures belong to the field of analog design, a circuit implementation is necessary in order to prove the superior performance of the novel architectures to the circuit designers community. Therefore, the preferred concept will be implemented in a 40nm CMOS technology by reusing as many of the previously designed circuitry as possible to reduce design time.

• DFG Programme: Research Grants