Highest-Linearity Nyquist Rate SAR ADCs in nm-CMOS - NanoSAR

• Applicant: Professor Dr.-Ing. Maurits Ortmanns
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2014 to 2021
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 245868713

• Final Report Year: 2021

Final Report Abstract

This project was the continuation of a previously very successfully conducted project, where our group could propose and prominently publish the combination of a power efficient SAR ADC with an incremental sigma-delta DAC, which realized an extended linearity in a high perfor- mance SAR. The continuation of the project was intended to find ways to speed up the operation, to find alternative ways to realize the I-SD DAC, and to analyze further high resolution, low noise, comparators. We could contribute publications on the topic of a new SMASH I-SD DAC, the input re- ferred noise of VCO based comparators, and the input referred noise of SAR ADC. Also, a prototype of a new SAR architecture based on a split C-DAC and based on pure I-SD DAC calibration could be realized in a 40nm CMOS technology. The chip is currently under measurement. It is operable, but not yet with full simulated specification. We hope to finalize the project after submission of this report with a successful measurement and a circuit based publication.

Publications

• “A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch”. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS). 2018, pp. 1–5
  Yanquan Luo et al.
  (See online at https://doi.org/10.1109/ISCAS.2018.8351088)
• “A Multi-bit Delta-Sigma DAC Architecture with Internal DAC Non-linearity Suppression”. In: Analogworkshop 2019, Universität Stuttgart. 2019
  Yanquan Luo, Ankesh Jain, and Maurits Ortmanns
  
• “Efficient High-Resolution Nyquist ADCs”. In: Next-Generation ADCs, High- Performance Power Management, and Technology Considerations for Advanced Integrated Circuits. Ed. by Dr. Andrea Baschirotto, Pieter Harpe, and Kofi A. A. Makinwa. Springer International Publishing, 2019
  P. Vogelmann et al.
  (See online at https://doi.org/10.1007/978-3-030-25267-0_3)
• “Input Referred Comparator Noise in SAR ADCs”. In: IEEE Transactions on Circuits and Systems II: Express Briefs 66.5 (2019), pp. 718–722
  Yanquan Luo et al.
  (See online at https://doi.org/10.1109/TCSII.2019.2909429)
• “Input Referred Noise of VCO-Based Comparators”. In: IEEE Transactions on Circuits and Systems II: Express Briefs 68.1 (2021), pp. 82–86
  Yanquan Luo and Maurits Ortmanns
  (See online at https://doi.org/10.1109/TCSII.2020.3008260)