Dynamically reconfigurable filters for digital signal processing with integrated circuits

• Applicant: Professor Dr.-Ing. Peter Zipf
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2014 to 2018
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 250645438

The goal of the proposed project is the development of optimization techniques for architectures to realize dynamically reconfigurable filters for digital signal processing. Dynamic reconfiguration allows to change the properties of filters during runtime. Such specialized filters are essential to cope with the rising complexity of advanced applications in information and communication technologies as well as advanced control applications. Having the possibility to adjust the requirements during runtime makes the use of dynamically reconfigurable filters more advantageous in comparison to conventional digital filters. Besides the decrease in complexity, a decrease in device costs and power consumption plays a major role. These design goals can be reached by applying the computer aided optimization of dynamically reconfigurable filters for freely programmable logic i.e. field programmable gate arrays (FPGAs), e.g. by the possibility of shared utilization of FPGA components, covered by the project. In this context both dynamic reconfiguration of logic by reconfigurable look-up tables and dynamic reconfiguration of the routing by multiplexers shall be optimized. Partial reconfiguration (PR) in Xilinx FPGAs will be applied in order to make comparisons. The destinated goal is to be able to generate optimized implementations of reconfigurable filters (concerning the requirements power consumtion, costs and performance) which can be used in future applications of digital signal processing and which extend the state of the art. The approaches to solution should be applicable for FPGAs and besides this for VLSI implementations in general.

• DFG Programme: Research Grants