PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

• Applicant: Professor Dr. Hans-Joachim Wunderlich
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2014 to 2018
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 256517186

• Final Report Year: 2019

Final Report Abstract

The simulation of circuits plays an important role during design and test validation of nanoelectronic circuits. Since designs produced in current technology nodes are getting more and more prone to subtle timing deviations caused by small delay defects, process variation and power issues (i.e., IR-drop), traditional validation methods relying on plain untimed logic simulation cannot provide meaningful results anymore. For this reason, expensive timing-aware simulation has become mandatory, which caused a sudden increase in the computational runtime complexity of the algorithms that quickly become inapplicable to designs with millions of gates. With the introduction of data-parallel compute architectures of the many-core era, such as graphics processing units (GPUs), new opportunities spawned for parallelizing algorithms to achieve higher simulation throughput and efficiency. For this reason, the DFG-project PARSIVAL (Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation) sought for novel simulation approaches that allow to utilize the high computing throughput of data-parallel architectures for developing scalable and timing-accurate validation tasks applicable to industrial-sized designs. Throughout the project phase, the first high-throughput logic-level time simulator for GPUs has been developed, which utilizes a multi-dimensional parallelization scheme. The developed timing-accurate simulation allows for waveform-accurate modeling of signals in time, with speedups exceeding three orders of magnitude (>1000×) compared to conventional commercial logic-level timing simulators. The accelerated simulation gives detailed insight into the distribution of circuit switching activity for individual test patterns for the application with low-power testing and also allows for broad variationaware investigation of small gate delay faults. The developed parallelization scheme was applied to construct a simulation model at switch level for GPUs, which allowed for waveform-accurate simulation of CMOS circuits based on first-order electrical parameters, which enabled capturing of CMOS- related delay effects that cannot be modeled at logic level in an efficient manner. This way, low-level parametric faults in CMOS cells can be modeled and simulated, without the need of logic abstraction and sacrificing the accuracy. The resulting switch level simulator outperforms commercial timing simulation at logic level by two orders of magnitude (>100×) despite its lower abstraction and higher precision. By combining similarities of both simulators, the very first GPU-accelerated timing-accurate multi-level simulation approach was developed. The multi-level simulation allows to trade-off speed and accuracy, which increases the simulation efficiency by allowing to save up to an order of magnitude in runtime by mixing abstractions. With the high-throughput parallelization concepts developed, timing-accurate evaluation with massive simulation speedup is achieved, which allows for new opportunities and novel design and test applications with new directions, that have previously been too expensive to realize. New directions comprise the development of more accurate algorithms and the extensive use of multi-level simulation for a holistic application to design and test validation, diagnosis as well as system-level test (SLT). The project PARSIVAL reached all the goals stated in the proposal, and its results exceeded the original expectations in terms of quantity and efficiency. The fast and precise simulation algorithms on the parallel architectures enabled a large amount of new applications and led to many national and international cooperation.

Publications

• GPU-Accelerated Small Delay Fault Simulation. In Proc. ACM/IEEE Conf. on Design, Automation Test in Europe (DATE), pages 1174–1179, Mar. 2015
  E. Schneider, S. Holst, M. A. Kochte, X. Wen, and H.-J. Wunderlich
  
• High-Throughput Logic Timing Simulation on GPG-PUs. ACM Trans. on Design Automation of Electronic Systems (TODAES), 20(3):37:1–37:21, Jun. 2015
  Stefan Holst, Michael E. Imhof, and Hans-Joachim Wunderlich
  
• Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. In Proc. IEEE 24th Asian Test Symp. (ATS), pages 103–108, Nov. 2015. ATS 2015 Best Paper Award
  K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, and J. Qian
  
• Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors. In Proc. IEEE Int’l Test Conf. (ITC), pages 1–7, Paper 3.4, Oct. 2017
  S. Holst, E. Schneider, K. Kawagoe, M. A. Kochte, K. Miyase, H.-J. Wunderlich, S. Kajihara, and X. Wen
  
• GPU-Accelerated Simulation of Small Delay Faults. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 36(5):829–841, May 2017
  E. Schneider, M. A. Kochte, S. Holst, X. Wen, and H.-J. Wunderlich
  
• SWIFT: Switch Level Fault Simulation on GPUs. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(1):122–135, Jan. 2019
  E. Schneider and H.-J. Wunderlich