Fastest Digital-to-Analog-Converter with low power consumption in FDSOI-CMOS Technology for Ultra-Broadband Data Transmission
Final Report Abstract
In optical communication networks, data rate increase is intended to be achieved by increasing symbol rate or channel bandwidth of one carrier, respectively, and by higher spectral efficiency using multi-level coherent modulation formats. The bottleneck of such systems are the electronic circuits rather than optical components and especially, the data converters being integrated on a single chip with digital signal processors in modern CMOS technologies. Moreover, in upcoming mobile and wireless networks with carrier frequencies above 100 GHz (e.g. 6G), transmission channels are getting more broadband. Therefore, digital-to-analog converters at very high conversion rates and high output bandwidth providing sufficient effective resolution at moderate power consumption are key components for a further increase of data rates in local as well as long-haul networks. The focus of this work is the implementation of a ultra-fast D/A converter in FD-SOI CMOS technology based on two novel topologies: 1. Two D/A output stages up to 64 GS/s being realized with unit cells consisting of static CMOS inverters and series resistors instead of commonly used switched current sources. Static CMOS supply voltage compatibility – in case of 28 nm CMOS technology 0.9 to 1.0 V – is one advantage of this concept. 2. Time-interleaving of two CMOS converter cores described in 1. by an active so-called 2-to-1 analog multiplexer. The latter consists of two linearized transconductance stages with current switches above, similar to two Gilbert cells, which act on a common output. To demonstrate the above mentioned D/A converter topology, a whole arbitrary waveform generator IC including a symbol memory of 256 kS à 8 bit has been developed in two iterations and in full-custom design methodology. Ultimately, a quite complex, fully-functional, ultra high-speed application-specific integrated circuit with more than 14 million MOSFETs resulted from this project. The project’s D/A converter was intended to support symbol rates up to 64 GBd corresponding to an available Nyquist bandwidth at the output of 32 GHz. In the measurements so far (as of 21/03/2022), symbol rates up to 80 GBd with 4-level pulse-amplitude modulation (PAM4) could be achieved corresponding to a bit rate of 160 Gbit/s and a Nyquist signal bandwidth of 40 GHz. The D/A converter exceeds the project’s goals as well as other published CMOS converters regarding Baud and data rate except intel’s converter having demonstrated 112 GBd PAM4 / 224 Gbit/s. However, this converter is implemented in an advanced 10 nm technology and packaged in a much more advanced flip-chip technology allowing very high bandwidths not reachable with classical bond wire packaging as used in this project where output bandwidth suffers from bond wires inductances. Moreover, it uses fourfold instead of twofold time-interleaving. Concerning maximum conversion rates, 100 GS/s could have been achieved so far in this project. It has to mentioned that the clock path functionality has been proved up to at least 57 GHz so far corresponding to a conversion rate of 114 GS/s. The operation field above 100 GS/s will be addressed in further, on-going measurements. To summarize, the measurements reveal the ability of the above mentioned circuit topologies to realize CMOS converters with performance parameters outperforming state-of-the-art converters of comparable CMOS nodes. Another insight is the importance of precise clock duty cycles of 50% for best output signal quality. For commercial use, the duty cycles would have to be set automatically by on-chip control circuits. Finally, for further conversion rate increase up to 160…200 GS/s, an architecture based on the presented components in combination with fourfold time-interleaving by a 4-to-1 analog multiplexer would be beneficial.
Publications
- „A Differential 19 Channel 64 Gbit/s 16:1 Multiplexer Including a Clock Network in a 28 nm CMOS Fully-Depleted Silicon-on-Insulator Technology“, in Kleinheubacher Tagung, U.R.S.I. Landesausschuss in der Bundesrepublik Deutschland e.V, Miltenberg, Germany, 2017, S. KH2017-Di-D1-02
D. Widmann, M. Grözing und M. Berroth
- „Speicher mit 1 Tbit/s Lesedurchsatz für einen sehr schnellen Arbiträrsignalgenerator in einer 28 nm FDSOI-CMOS-Technologie“, in Kleinheubacher Tagung, U.R.S.I. Landesausschuss in der Bundesrepublik Deutschland e.V, Miltenberg, Germany, 2017, S. KH2017-Di-D1-01
T. Veigel, S. Brandl und M. Grözing
- „High-Speed Serializer for a 64 GS s-1 Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology“, Advances in Radio Science, Bd. 16, S. 99-108, 2018
D. Widmann, M. Gözing und M. Berroth
(See online at https://doi.org/10.5194/ars-16-99-2018) - „Multi-Phase Clock Path Circuit up to 57 GHz Including 5 bit Programmable Phase Interpolators for Time-Interleaved Broadband Data Converters in a 28 nm FD- SOI CMOS Technology”, European Microwave Integrated Circuits Conference (EuMIC) 2021
D. Widmann, T. Tannert, X.-Q. Du, M. Grözing und M. Berroth
(See online at https://doi.org/10.23919/EuMIC50153.2022.9783934)
