PARFAIT II: Power-aware AmbipolaR Fpga ArchITecture II

• Applicants: Professor Dr.-Ing. Jürgen Becker; Professor Dr.-Ing. Klaus Hofmann; Professor Dr.-Ing. Thomas Mikolajick
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering ; Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2017 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 326384402

In PARFAIT II, planar reconfigurable field-effect transistors (RFETs) with electrically adjustable p- and n-conductivity are being researched. While PARFAIT I explored the technological fundamentals of these ambipolar transistors largely by simulation, the focus of PARFAIT II is on the fabrication of the transistors, the development of logic gates and their use in complex circuits. For this purpose, a reliable and reproducible fabrication process for planar RFETs has to be designed and questions regarding the stabilization of the Schottky contacts and electrical symmetry of the RFET have to be answered. Following a joint specification phase, the simulative models from PARFAIT I will be verified and adapted to real manufacturing conditions by designing, manufacturing and measuring test circuits. The aim is to develop an efficient compact model that reflects the dynamic reconfigurability, incorporates parasitic effects and still allows short simulation times. The foundations will be laid to be able to use reconfigurable transistors in real applications with scaled geometries on a larger scale.Further, PARFAIT II will investigate circuit- and system-level applications for which the simulated and measured characteristics of the RFETs explored are most promising. In addition to dynamically changing the switching function of logic gates, these are primarily the space-saving realization of logic-in-memory cells and the use in analog circuits (e.g. BPSK modulators). A major part of the project is the investigation of the temperature behavior of the RFET from the technology to the system level: Since no doping is used for the fabrication of RFETs, it is obvious that RFETs can be operated in wider temperature ranges than conventional CMOS circuits. Since pure simulations do not provide reliable results here, PARFAIT II will perform measurements in the range of 70K to 200K and extend them down to 4K if the results are positive. If circuits are operated over such wide temperature ranges, various effects can be expected to influence the signal propagation times. Therefore, a dynamic compensation of these effects will be investigated on circuit and system level, especially for an FPGA architecture based on RFETs: The reconfigurability of the FPGA circuit will be used to dynamically reconfigure parts of the FPGA for measuring the signal propagation times. According to the measurements, the capability of the planar RFETs is used to adapt threshold voltages, leakage currents and switching currents of cells in a fine-granular way via the additional back gate, independent of the configured logic function (set via the front gates). This approach is intended to compensate for temperature and process influences, especially with regard to extreme operating environments.

• DFG Programme: Research Grants
• Co-Investigator: Dr.-Ing. Jens Trommer