Technology-aware Asymmetric 3D-Inteconnect Architectures: Templates and Design Methods

• Applicants: Professor Dr. Alberto Garcia-Ortiz; Professor Dr.-Ing. Thilo Pionteck
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2017 to 2021
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 328514428

New production methods enable the design of heterogeneous 3D-System-on-Chips (3D-SoCs), which consist of stacked silicon dies manufactured with different technologies. In contrast to homogeneous SoCs, this allows to adjust the technological characteristics of each die to the specific requirements of the components placed in each layer. Heterogeneous 3D-SoCs provide unprecedented integration possibilities for embedded and high performance systems. To exploit that potential, powerful, flexible, and scalable communication infrastructures are required. Yet, current interconnect architectures (IAs) tacitly assume a multilayer homogeneous 3D-SoC and do not consider the influence of different technology parameters on the topology, architectural, and micro-architectural level of the IA.In this project, we aim to develop architectural templates and design methods for 3D-interconnect architectures for heterogeneous 3D-SoCs. We target two main innovations: First, we will exploit the specific technology characteristics of individual chip layers in heterogeneous 3D-SoCs. Therefore, we will re-evaluate and extend existing approaches for heterogeneous and hybrid 2D-interconnect architectures. Second, we aim at discovering new interaction mechanisms among components, which may be spatially distributed even at the micro-architectural level, to exploit their diverse features when manufactured in different technologies. The combination of these aspects leads to technology asymmetric 3D-interconnect architectures (TA-3D-IAs), as defined in this proposal for the first time.The main outcome of the project will be a deeper understanding of TA-3D-IAs as part of heterogeneous 3D-SoCs. Further, we will develop systematic design methodologies and a set of architectural templates for the design of TA-3D-IAs. Therefor we will create a full-fledged simulation framework for the analysis of TA-3D-IAs' design space, which will be capable of accounting for technology-specific parameters for all components of the communication infrastructure. In addition, we will provide reference benchmarks and selected TA-3D-IAs, which will allow other research teams to evaluate and compare their ideas.

• DFG Programme: Research Grants