Technology-aware Asymmetric 3D-Inteconnect Architectures: Templates and Design Methods
Final Report Abstract
The aim of this project was to develop architectural templates and design methods for 3D-interconnect architectures suited for technology-asymmetrical 3D System on a Chip (3D SoCs). By exploiting the specific technology characteristics of individual chip layers in heterogeneous 3D SoCs we targeted two main innovations: First, we re-evaluated and extended existing approaches for heterogeneous and hybrid 2D interconnect architectures by incorporating technology characteristics of heterogeneous 3D SoCs. Second, we aimed at discovering new interaction mechanisms among components, which are spatially distributed even at the micro-architectural level to exploit their diverse features when manufactured in different technologies. The combination of these aspects leads to technology asymmetric 3D-interconnect architectures (TA-3D-IAs), which incorporate distributed interconnect components among layers, specialized communication infrastructure per layer as well as specialized inter-layer links using through-silicon via (TSVs). With this project, we have provided a comprehensive and unique approach for the modeling and optimization of interconnect architectures in 3D SoCs at all abstraction levels, specifically addressing the challenges and opportunities arising from heterogeneous stacking. Thereby, it improves the most relevant quality metrics: throughput, power consumption, area, and yield. Specifically, we contribute to the state-of-art in the following fields: 1. Modeling and optimization techniques for technological and system-level aspects, hardware architectures, and physical-design tools. 2. Abstract but yet physically precise models for the power-consumption and performance of TSV-based 3D interconnects to optimize and evaluate interconnect architectures for 3D SoCs. 3. A wide set of generic ready-to-use optimization techniques which substantially improve power consumption, performance, and yield of TSV-based 3D interconnects, while exploiting key characteristics of heterogeneous integration. 4. Novel architectures for 3D Network on a Chip (3D NoC) using heterogeneous integration, providing higher network performance at a lower power-consumption and area. 5. An open-source NoC simulator and optimization tool for heterogeneous SoC architectures. The results corroborate our hypothesis that existing interconnect architectures, and in particular existing NoCs, have not fully exploited the intrinsic technology asymmetry present in heterogeneous 3D SoCs. We have shown that the additional degrees of freedom for system design provided by the specific characteristics of individual technology layers have a dramatic impact to improve the power, performance and area in 3D architectures.
Publications
- “High-Level Energy Estimation for Submicrometric TSV Arrays”. In: IEEE Trans. on VLSI Systems 25.10 (Oct. 2017), pp. 2856–2866
L. Bamberg and A. Garcia-Ortiz
(See online at https://doi.org/10.1109/TVLSI.2017.2713601) - “Coding Approach for Low-Power 3D Interconnects”. In: 2018 55th IEEE Design Automation Conference (DAC). 2018, pp. 1–6
L. Bamberg, R. Schmidt, and A. Garcia-Ortiz
(See online at https://doi.org/10.1109/DAC.2018.8465767) - “Edge effects on the TSV array capacitances and their performance influence”. In: Integration 61 (2018), pp. 1–10
L. Bamberg, A. Najafi, and A. García-Ortiz
(See online at https://doi.org/10.1016/j.vlsi.2017.10.003) - “Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs”. In: IEEE Trans. on VLSI Systems 27.10 (2019), pp. 2317–2330
L. Bamberg and A. Garcia-Ortiz
(See online at https://doi.org/10.1109/TVLSI.2019.2923633) - “NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures”. In: IEEE Access 7 (2019), pp. 135145–135163
J. M. Joseph, L. Bamberg, D. Ermel, B. R. Perjikolaei, A. Drewes, A. García-Ortiz, and T. Pionteck
(See online at https://doi.org/10.1109/ACCESS.2019.2942129) - “Simulation environment for link energy estimation in networks-on-chip with virtual channels”. In: Integration 68 (2019), pp. 147 –156
J. M. Joseph, L. Bamberg, I. Hajjar, R. Schmidt, T. Pionteck, and A. García-Ortiz
(See online at https://doi.org/10.1016/j.vlsi.2019.05.005) - “Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures”. In: ASP-DAC. IEEE. 2021
J. M. Joseph, L. Bamberg, J. Geonhwa, Ruei-Ting Chien, Rainer Leupers, Alberto García-Oritz, Tushar Krishna, and Thilo Pionteck
(See online at https://doi.org/10.1145/3394885.3431421) - “Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs”. In: ACM Trans. Model. Comput. Simul. 32.1 (Sept. 2021)
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García-Ortiz, and Thilo Pionteck
(See online at https://doi.org/10.1145/3472754)
