TraceSymm: Trace analysis and Symmetry theory for improved application mapping onto manycores

• Applicant: Professor Dr.-Ing. Jeronimo Castrillon-Mazo
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2017 to 2023
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 366764507

• Final Report Year: 2024

Final Report Abstract

The diminishing returns in single-core architectures around 2005 marked an inflection point in computing systems. Since then, multi-cores in all kinds of devices proliferated, causing a boom in models and methodologies focused on how to efficiently program parallel architectures. While industry opted for extensions to established languages (e.g., OpenMP), programming models with formal properties are more popular in academia. In particular, dataflow programming models from the 1970s recently regained interest and are today a matter of a large body of research in the embedded and general purpose domains. A central research problem is that of computing an optimal mapping from a high-level application description to a parallel hardware platform, including the placement of computation to cores, communication to memories and interconnect, and deciding on the execution order. Applications have evolved so that they cannot always be described by static models, i.e., for which static analysis suffices to compute an optimal mapping. A common approach to handle this dynamism consists in analyzing execution traces of an application to better tailor the mapping. With upcoming larger systems and more dynamic applications it is essential to improve trace analysis and trace-based mapping methodologies. In this project we (i) studied dynamic dataflow graphs in the context of 4G/5G networks, (ii) developed adaptive mappings that change with variation in the workload, (iii) developed a framework for the characterization and exploitation of problem symmetries, (iv) developed novel compile-time and runtime mapping algorithms that leverage the problem symmetries, (v) contributed an open source framework with all the methods for extensibility and reproducibility.

Publications

• Symmetry in Software Synthesis. ACM Transactions on Architecture and Code Optimization, 14(2), 1-26.
  Goens, Andrés; Siccha, Sergio & Castrillon, Jeronimo
  
• TETRiS. Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 11-20. ACM.
  Goens, Andrés; Khasanov, Robert; Castrillon, Jeronimo; Hähnel, Marcus; Smejkal, Till & Härtig, Hermann
  
• On Compact Mappings for Multicore Systems. Lecture Notes in Computer Science, 325-335. Springer International Publishing.
  Goens, Andrés; Menard, Christian & Castrillon, Jeronimo
  
• Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade. Proceedings of the IEEE, 108(8), 1303-1321.
  Blasing, Robin; Khan, Asif Ali; Filippou, Panagiotis Ch.; Garg, Chirag; Hameed, Fazal; Castrillon, Jeronimo & Parkin, Stuart S. P.
  
• Modem Design in the Era of 5G and Beyond: The Need for a Formal Approach. 2020 27th International Conference on Telecommunications (ICT), 1-5. IEEE.
  Wittig, Robert; Goens, Andres; Menard, Christian; Matus, Emil; Fettweis, Gerhard P. & Castrillon, Jeronimo
  
• Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories. ACM Transactions on Embedded Computing Systems, 19(6), 1-26.
  Khan, Asif Ali; Rink, Norman A.; Hameed, Fazal & Castrillon, Jeronimo
  
• Polyhedral Compilation for Racetrack Memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3968-3980.
  Khan, Asif Ali; Mewes, Hauke; Grosser, Tobias; Hoefler, Torsten & Castrillon, Jeronimo
  
• BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory. 2021 58th ACM/IEEE Design Automation Conference (DAC), 1111-1116. IEEE.
  Hakert, Christian; Khan, Asif Ali; Chen, Kuan-Hsun; Hameed, Fazal; Castrillon, Jeronimo & Chen, Jian-Jia
  
• Domain-specific Hybrid Mapping for Energy-efficient Baseband Processing in Wireless Networks. ACM Transactions on Embedded Computing Systems, 20(5s), 1-26.
  Khasanov, Robert; Robledo, Julian; Menard, Christian; Goens, Andrés & Castrillon, Jeronimo
  
• Mocasin—Rapid Prototyping of Rapid Prototyping Tools. Proceedings of the 2021 Drone Systems Engineering and Rapid Simulation and Performance Evaluation: Methods and Tools Proceedings, 66-73. ACM.
  Menard, Christian; Goens, Andrés; Hempel, Gerald; Khasanov, Robert; Robledo, Julian; Teweleitt, Felix & Castrillon, Jeronimo
  
• Embeddings of Task Mappings to Multicore Systems. Lecture Notes in Computer Science, 161-176. Springer International Publishing.
  Goens, Andrés & Castrillon, Jeronimo
  
• mpsym: Improving Design-Space Exploration of Clustered Manycores With Arbitrary Topologies. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(6), 1592-1605.
  Goens, Andres; Nicolai, Timo & Castrillon, Jeronimo
  
• ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees. IEEE Transactions on Computers, 72(5), 1488-1502.
  Hakert, Christian; Khan, Asif Ali; Chen, Kuan-Hsun; Hameed, Fazal; Castrillon, Jeronimo & Chen, Jian-Jia