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X-ReAp: Cross(X)-Layer Runtime Reconfigurable Approximate Architecture

Subject Area Computer Architecture, Embedded and Massively Parallel Systems
Term from 2017 to 2022
Project identifier Deutsche Forschungsgemeinschaft (DFG) - Project number 380524764
 
The paradigm of approximate computing has emerged as a viable solution for realizing high-performance and energy-efficient hardware accelerators for error-resilient applications. In the DFG-funded project ReAp: Runtime Reconfigurable Approximate Architecture, our team has successfully achieved the milestones of the project since its start in 2018. These achievements include the novel designs of various accurate and approximate arithmetic modules (adders, compressors, multipliers, and dividers), low bit-width quantization techniques, and platform-level support for run-time approximations. The proposed open-source libraries of approximate arithmetic modules support design- and run-time accuracy-performance trade-offs. Our proposed quantization schemes produce insignificant accuracy loss in output quality and provide more resource gains than state-of-the-art techniques. Further, the developed platform-level support performs the automated placement of various modules onto a combination of mixed-sized reconfigurable regions. These achievements have been acknowledged and published at top IEEE/ACM conferences like DAC, DATE, ASPDAC, and journals like TC and TCAD. Most state-of-the-art works in the domain of approximate computing have focused on individual layers of the computation stack. However, during the course of ReAp project, we have discovered the enormous potential of realizing energy-efficient and high-performance approximate hardware accelerators by analyzing and combining approximations on multiple layers (cross-layer approximation) of the computation stack. Compared to the approximations at a single-level, the cross-layer approximation can provide more design points with better accuracy-performance trade-offs. Towards this end, in this project (X-ReAp), we will develop a framework to partition an input application into multiple sub-tasks. The framework will utilize various machine learning (ML) models to analyze the impact of various high-level approximations, at the sub-tasks level, on the application's overall output quality and performance. For example, for convolution operator-based applications, it can analyze the required precision, window size, and stride length to satisfy the application's accuracy and performance constraints. We will then use various ML techniques to analyze the impact of approximate arithmetic modules on the output accuracy and performance of each sub-task. This information will be used by our framework to provide feasible design points (accelerator configurations) satisfying the overall accuracy and performance constraints. This will also help support the hardware accelerator's run-time adaptations by loading a new accelerator configuration when the accuracy/performance requirements change dynamically. The whole methodology and the framework will be evaluated with real applications from two different domains - health monitoring and scene perception for autonomous vehicles.
DFG Programme Research Grants
 
 

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