Integrated Memristor-Based Computer Architectures
Final Report Abstract
The project "IMBRA - Integrated Memristor-based Computer Architectures" pursued the goal to advance computing with memristors (Memristive Computing), in this case concretely for the example of ReRAM-technologies, which was available for the project at the IHP – the Leibniz Institute for High-Performance Microelectronics. Until the start of the project the solutions for memristive computing known from the literature have been mostly focused on the basic feasibility of individual Boolean operators such as AND, OR, etc.. Whereas the IMBRA project wanted to go a step further, both conceptually and technologically, with the design of adders and their intended prototypical realization. An important qualitative focus was the exploitation of the multibit property of ReRAMs to build carry-free adders operating on ternary operands, which conventional memory technology in principle cannot do as efficiently as ReRAMs. To achieve these goals, IMBRA conducted research in three areas: (i) at the device level, basic circuits for reading and writing multibit ReRAMs were developed for the first time in IHP technology and were realized as a prototype chip in 130nm technology. (ii) Furthermore, on the circuit level, different suitable circuits for the evaluation of the ternary operands close to the memory (in-memory computing) were designed and verified by simulation, in order to obtain more energy-efficient arithmetic circuits in the future than at present by exploiting ReRAM technology. (iii) In a further step on the architectural level, it was investigated in detail how a future processor working on ternary data paths, in this case based on the open RISC- V instruction set, has to look like in order to exploit the potential of ReRAMs for multibit storage and carry-free arithmetic for computing technology in general. With respect to the achieved results and their sustainability, the following emerged. (i) On the device level, IMBRA has gained important insights for the ReRAM technology for the technology location Germany, especially concerning the topic of reading and writing of multibit states in ReRAMs. (ii) If this technology is further developed and improved, circuits and processing concepts are now available through IMBRA, which enables more energy-efficient adders in the future, if these circuits are connected to the readout circuitry for ReRAMs found in IMBRA, too. In a further step, these solutions, verified by simulation in IMBRA, must now be implemented and tested in real chips. After steps (i) and (ii) have been completed, step (iii) provides a blueprint of how this can be profitably used in a future complete processor architecture.
Publications
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A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability. IEEE Transactions on Nanotechnology, 18(2019), 647-656.
Reuben, John; Fey, Dietmar & Wenger, Christian
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A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM. 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 1-6. IEEE.
Reuben, John & Fey, Dietmar
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“Optimizing Multi-State Reliability in ReRAM Arrays Using an Automated Device Selection Method”, Memrisys-Workshop, Dresden 2019
Peschel, J.; Knödtel, J.; Perez, E.; Reichenbach, M.; Wenger, C. & Fey, D.
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Direct state transfer in MLC based memristive ReRAM devices for ternary computing. 2020 European Conference on Circuit Theory and Design (ECCTD), 1-5. IEEE.
Fey, Dietmar & Reuben, John
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Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford–PKU Model. IEEE Transactions on Nanotechnology, 19(2020), 508-518.
Reuben, John; Biglari, Mehrdad & Fey, Dietmar
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A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells. Electronics, 10(5), 530.
Pechmann, Stefan; Mai, Timo; Völkel, Matthias; Mahadevaiah, Mamathamba K.; Perez, Eduardo; Perez-Bosch, Quesada Emilio; Reichenbach, Marc; Wenger, Christian & Hagelauer, Amelie
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Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 157-163. IEEE.
Reuben, John & Fey, Dietmar
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RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems. IEEE Access, 9(2021), 43684-43700.
Reichenbach, Marc; Knodtel, Johannes; Rachuj, Sebastian & Fey, Dietmar
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Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), 1-4. IEEE.
Fritscher, Markus; Knödtel, Johannes; Reiser, Daniel; Mallah, Maen; Pechmann, Stefan; Fey, Dietmar & Reichenbach, Marc
