Intrinsically Linear Incremental Sigma-Delta Converters - iLIDS

• Applicant: Professor Dr.-Ing. Maurits Ortmanns
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2018
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 390567189

Incremental Sigma-Delta Analog-digital Converters (I-SD ADC) combine the advantages of two worlds. They rely on oversampling and noise-shaping, and still they serve as true Nyquist rate converters and can thus be time-interleaved or multiplexed. This is achieved with a periodic reset.While I-SD ADC have been implemented in the past for very high resolution, but very low speed e.g. sensor interfaces, more recently higher bandwidth converters have been shown, which also employ the more power efficient continuous-time (CT) implementation of the loop filter. In order to achieve even higher bandwidth, a realization of internal multibit quantization comes as a necessity, as oversampling ratio (OSR) must be reduced. Multibit quantization concurrently allows more stable system operation, more aggressive loop filter scaling, more maximum stable amplitude (MSA) and less dynamic requirements on the amplifiers. But it comes with the tremendous disadvantage of non-linearity in the feedback digital-analog converter (DAC). In a first project phase, we have proposed an architecture, the I-SMASH, which allows multibit operation and DAC while not suffering from DAC non-linearity by dynamically reconfiguring the operation. Also, the employment of FIR DACs was introduced and ISI analyzed. A prototype implementation could be prominently published. Though, it came with the disadvantage, that stability, MSA, jitter and intersymbol interference (ISI) sensitivity are defined in the first, single-bit phase, whereas only the quantization noise performance is advantageously defined in the 2nd multibit phase.In the presented project proposal, we want to extend the findings of the first phase. An intrinsically linear 5-level switched capacitor (SC) DAC shall be employed, which is analyzed under the influence of CT loop filter operation and finite bandwidth of the amplifiers. It is modified to allow low dynamics and low sensitivity to jitter and ISI. We will employ variants of the SC DAC to achieve this. Time interleaving to achieve more levels, current starving to reduce peak currents, FIR DAC implementation to reduce dynamics further. Additionally, the project will extent the prior work by employing noise coupled SAR based internal quantization, in order to allow higher order loop filtering in both stages of I-SMASH. Finally, the concept of fractional sequencing will be modified to be able to employ it in dynamically reconfigured I-SD ADC together with COI reconstruction filters. Fractional sequencing, a general form of chopping, will thereby allow to reduce the influence of low frequency noise as well as to eliminate offset.

• DFG Programme: Research Grants