Reconfigurable Field-Effect-Transistors
Final Report Abstract
Several research approaches to further increase the performance of highly integrated circuits are currently pursued. One promising approach is to increase the functionailty on the level of the individual devices. This means, instead of realizing only one type of transistor fixde to work as a switch yielding two logic states, devices that could be tuned in their functionality would enable to use certain areas of a chip to implement different logic functions and also to realize logic with multiple output with a reduced number of transistors (compared to an implementation in standard CMOS technology). Such devices are called reconfigurable transistors since their function can be switched or reconfigured to operate them as p-type or n-type (and even socalled band-to-band tunnel FETs would be possible). Several implementations based in different semiconductors have been demonstrated and characterized in literature so far. However, all of them share a common, major drawback: to enable reconfigurability, charge carriers are injected from a metal into the semiconductor through a Schottky-barrier. And in order to obtain a more or less symmetric functionality for n- and p-type device this Schottkybarrier needs tob e similar in both cases of electron and hole injection which basically strongly deteriorates the current drive capacbility of both configurations oft he device. The aim of the current project was to remove the injection through a Schottky-barrier and allow for gatetunable, reconfigurable contacts. To this end, a stack consisting of the semiconductor (silicon in the present case), an ultrathin silicon nitride layer that prevents the silicon from oxidizing (which would result in a substantial potential barrier) and removes the so-called Fermi level pinning, a monolayer graphene, followed by a gate dielectric and a gate electrode. With appropriate layer thicknesses the top gate electrode is capable to manipulate the semiconductor (silicon) through the field-effect. This is possible, since the graphene layer exhibits a very small density of states around ist Dirac point, such that the electric field between silicon and top-gate is not screened. However, for sufficiently large gate voltages, the conduction/valence bands of the graphene are also shifted in energy leading to an approximately linearly increasing charge carrier density. This carrier density screens the gate impact but renderst he graphene metallic such that charge can be injected through the ultrathin silicon nitride into the semiconductor. In the case of a sufficiently long contact and appropriately thin silicon nitride, excellent carrier injection far better than through a Schottky-barrier can be expected. The realization of the targeted device, i.e. a field-effect transistor with a graphene reconfigurable contact required the development of a number of process modules. In particular, the formation of a proper, ultrathin Fermi level depinning SiN layer is needed. To this end, hydrogen annealing has been tested. Further process modules include appropriate substrates that provide active areas that are insulated from each other but also enable visibility of graphene, the transfer of graphene and eventually a proper gate insulator consisting of Al2O3 deposited with atomic layer deposition. All process modules could be implemented successfully and parts of the results have been published in scientific journals. Integrating all process modules into a single device has failed so far. During the course oft he project an additional use of the ultrathin silicon nitride films could be identifiied namely the surface passivation of silicon in ordert o prevent its oxidation during the deposition of a high-k gate dielectric. Interestingly, while silicon nitride results in an interface density of states which is unfavorable for room temperature electronics, it is very well suited for cryogenic CMOS devices yielding superior switching behavior.
Publications
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Silicon Nitride Interface Engineering for the Realization of Dopant Free MOSFETs, Spring Meeting of the German Physical Society 2019
B. Richstein, L. Hellmich & J. Knoch
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Towards Dopant-free MOSFETs by Silicon Nitride Interface Engineering, Spring Meeting of the German Physical Society 2019
L. Hellmich, B. Richstein & J. Knoch
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Employing CMOS technology on silicon for a scalable electron-spin qubit architecture Bulletin APS 66 (2021)
J. Klos, B. Sun, J. Beyer, S. Kindel, L. Hellmich, J. Knoch & L. Schreiber
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Silicon Nitride Interface Engineering for Fermi Level Depinning and Realization of Dopant-Free MOSFETs. Micro, 1(2), 228-241.
Richstein, Benjamin; Hellmich, Lena & Knoch, Joachim
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Cryogenic Steep Slope Field-Effect Transistors. 2022 IEEE Silicon Nanoelectronics Workshop (SNW), 1-2. IEEE.
Knoch, J.; Richstein, B.; Han, Y.; Konig, D.; Frentzen, M.; Hellmich, L.; Klos, J.; Scholz, S. & Zhao, Q.T.
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Interface Engineering for Steep Slope Cryogenic MOSFETs Device Research Conference 2022
B. Richstein, Y. Han, L. Hellmich, J. Klos, L. Schreiber, Q.T. Zhao, S. Scholz & J. Knoch,
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Interface Engineering for Steep Slope Cryogenic MOSFETs. IEEE Electron Device Letters, 43(12), 2149-2152.
Richstein, B.; Han, Y.; Zhao, Q.; Hellmich, L.; Klos, J.; Scholz, S.; Schreiber, L. R. & Knoch, J.
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Miniaturized pH‐Sensitive Field‐Effect Capacitors with Ultrathin Ta2O5Films Prepared by Atomic Layer Deposition. physica status solidi (a), 219(8).
Molinnus, Denise; Iken, Heiko; Johnen, Anna Lynn; Richstein, Benjamin; Hellmich, Lena; Poghossian, Arshak; Knoch, Joachim & Schöning, Michael J.
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Steep Slope Transistors for Cryogenic Electronics”, Fall Meeting of the European Materials Research Society, Warsaw, 2022
J. Knoch, B. Richstein, Y. Han, D. König, M. Frentzen, N. Wilck, L. Hellmich, J. Klos, L. Schreiber, S. Scholz & Q.T. Zhao
