Unlocking Analog Features and Full Parallelism for HDL-based Synthesis of PLiM

• Applicants: Professor Dr. Rolf Drechsler; Dr. Saeideh Shirinzadeh
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: since 2019
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 406079023

In-memory computing enabled by advanced non-volatile memory technologies is a promising paradigm for the known issue of von Neumann bottleneck in current computing systems. However, the capacity of in-memory computing for logic design has not been fully explored. This proposal includes six work packages that contribute to the advancement and comprehensiveness of design automation for logic-in-memory computer architectures based on standard crossbars of Resistive RAM (RRAM). This research plan aims at enhancing the performance of resistive logic-in-memory computer architectures by creating new capacity for parallelism, developing new features based on the inherent analog computation capability of RRAM and approximate computing. Furthermore, we aim at adding these new elements to the Logic-in-Memory Hardware Description Language (LiM-HDL), which has been developed in the initial phase of the project.

• DFG Programme: Research Grants