Gegenüberstellung von evolutionären Algorithmen und maschinellen Lernverfahren für energiebewusstes Instruction Scheduling
Elektronische Halbleiter, Bauelemente und Schaltungen, Integrierte Systeme, Sensorik, Theoretische Elektrotechnik
Zusammenfassung der Projektergebnisse
Current digital signal processors (DSP) take profit of a very long instruction word (VLIW) architecture style, which provides high performance by executing independent instructions in parallel, and reduced power consumption due to the small silicon area requirement compared to other parallel processor architecture concepts. For that, VLIW-DSP compiler backends are in charge of rearranging independent instructions of the input program into very long instructions. In this project, a new evolutionary-based instruction scheduler and register allocation was proposed. This open-source VLIW-DSP retargetable compiler backend implements a genetic algorithm to search for a minimal compaction code, allowing to naturally consider all the intrinsic features of a chosen target architecture and obtaining better results than traditional heuristicbased approaches. In real-time applications, a better code compaction is directly translated into a reduction in the processorâs clock frequency needed to process the input data in a specified time. For an exemplary application, i.e., noise reduction of digital audio signals for hearing aid devices, the use of our evolutionary-based instruction scheduling approach shows that the performance (by means of clock requirement reduction) can increase up to 13.6% in comparison to the standard heuristic-based scheduling, i.e., list-scheduling algorithm, while the compile time increases exponentially and can reach up to 23.5 hours. Moreover, an evaluation of the proposed VLIW-DSP retargetable compiler backend was presented in two PhD-theses for different applications fields, i.e., for advanced driver assistance systems and for hearing aid devices. Finally, a second open-source tool for verifying and validating processor architectures, called PATARA, was also implemented and used to test the proposed VLIW-DSP retargetable compiler backend. Power reduction can be also reached with the help of the VLIW-DSP compiler backend, by using an energy consumption model of the register file access, i.e., a register address transition energy model, during the register allocation and instruction scheduling. A multi-objective evolutionary algorithmic approach was implemented inside the VLIW-DSP retargetable compiler backend and was evaluated with an exemplary VLIW-DSP processor architecture. The results show that in synthetic applications with random data in the register file, the dynamic energy consumption of the total processor core can be reduced by up to 21% compared to a traditional heuristicbased register allocation. In applications from the domain of hearing aid devices, the energy consumption can be reduced up to 20% compared to a heuristic-based instruction scheduling and register allocation, i.e., list scheduling algorithm and register balancing approach, respectively. The proposed evolutionary-based VLIW-DSP compiler backend can obtain better performance results than heuristic-based ones. However, these improvements are associated with long compiling times, i.e., from hours to days. As a second goal in this project, a machine learning approach was studied to decrease the compilation time. The idea is to learn from the evolutionary-based approach and to generate better heuristic functions that can better prioritize the scheduling of the instructions or the physical allocation of the registers. The results show that the use of a graph neural network to schedule the instructions of a VLIW-DSP processor architecture presents similar compaction code than the traditional list-scheduling approach, but reduces the register file pressure, allowing to schedule more assembly programs without requiring the use of a register spilling approach (and its derived decrease of performance/code compaction).
Projektbezogene Publikationen (Auswahl)
-
Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers. Journal of Signal Processing Systems, 92(7), 655-678.
Giesemann, Florian; Gerlach, Lukas & Payá-Vayá, Guillermo
-
PATARA Repository. Chair for Chip Design for Embedded Computing, Technische Universität braunschweig, 2021.
Fabian Stuckmann & Guillermo Payá-Vayá
-
PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores. 2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST), 1-6. IEEE.
Stuckmann, Fabian; Fistanto, Pasha A. & Paya-Vaya, Guillermo
-
TUKUTURI: eine dynamisch selbstrekonfigurierbare Softcore Prozessorarchitektur. PhD Thesis (Supervisor: Prof. Payá-Vayá). 2021.
Florian Giesemann
-
“KAVUAKA: A Low-Power Application-Specific Processor Architecture for Digital Hearing Aids”. PhD Thesis (Supervisor: Prof. Payá-Vayá). Leibniz Universität Hannover, 2021.
Lukas Gerlach
-
Instruction Scheduling Repository. Chair for Chip Design for Embedded Computing, Technische Universität braunschweig, 2022.
Fabian Stuckmann, Florian Giesemann & Guillermo Payá-Vayá
